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PDF ( 数据手册 , 数据表 ) ADD8754

零件编号 ADD8754
描述 Gate Modulation
制造商 Analog Devices
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ADD8754 数据手册, 描述, 功能
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FEATURES
Step-up switching regulator with 2 A power switch
650 kHz or 1.2 MHz switching frequency
Output adjustable to 20 V
350 mA logic voltage regulator
Selectable output voltages: 2.5 V, 2.85 V, 3.3 V
VCOM amplifier with 300 mA drive
Gate pulse modulation circuitry
Independently adjustable delay and falling slope
General
3 V to 5.5 V input
Undervoltage lockout
Thermal shutdown
24-lead, Pb-free LFCSP package
APPLICATIONS
TFT LCD panels for monitors, TVs, and notebooks
GENERAL DESCRIPTION
The ADD8754 is optimized for use in TFT LCD applications,
requiring only external charge pump components to provide all
the requirements for panel power, VCOM, and gate modulation.
Included in a single chip are a high frequency step-up dc-to-dc
switching regulator, logic voltage regulator, VCOM amplifier, and
gate pulse modulation circuitry.
The step-up dc-to-dc converter provides up to 20 V output and
includes a 2 A internal switch. Either a 650 kHz or 1.2 MHz step-
up switching regulator frequency can be chosen, allowing easy
filtering and low noise operation. It achieves 93% efficiency and
features soft start to limit the inrush current at startup.
The internal voltage regulator operates with an input voltage
range of 3 V to 5.5 V and delivers a load current of up to
LCD Panel Power, VCOM,
and Gate Modulation
ADD8754
FUNCTIONAL BLOCK DIAGRAM
COMP SS VIN_1 VIN_2
FB
FREQ
SHDN
ADD8754
STEP-UP SWITCHING
REGULATOR
LX
UNDER VOLTAGE LOCKOUT
AND THERMAL PROTECTION
VDD_2
OUT
LOGIC VOLTAGE
REGULATOR
VCOM AMPLIFIER
LDO_OUT
ADJ
POS
NEG
GATE PULSE
MODULATION
VGH VGH_M VDD_1 CE RE VFLK VDPM
Figure 1.
350 mA. Three selectable output voltages are available: 2.5 V,
2.85 V, and 3.3 V.
The proprietary VCOM amplifier can deliver a peak output
current of 300 mA and is specifically designed to drive TFT
panel loads.
The gate pulse modulator allows shaping of the TFT gate high
voltage to improve image quality. The integrated switches
provide the ability to independently control the delay and slope
for the gate drive voltage.
The ADD8754 is offered in a 24-lead, Pb-free LFCSP package and
is specified over the industrial temperature range of −40 to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2005 Analog Devices, Inc. All rights reserved.







ADD8754 pdf, 数据表
ADD8754
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
24 23 22 21 20 19
GND 1
VGH_M 2
VFLK 3
VDPM 4
VDD_1 5
VDD_2 6
ADD8754
TOP VIEW
(Not to Scale)
18 LX
17 VIN_2
16 FREQ
15 COMP
14 SS
13 VIN_1
7 8 9 10 11 12
Figure 2. Pin Configuration
Table 7. Pin Function Descriptions
Pin Mnemonic Description
1 GND
Ground.
2 VGH_M
Gate Pulse Modulator Output. This pin supplies the gate drive signal.
3 VFLK
Gate Pulse Modulator Control Input.
4 VDPM
Gate Pulse Modulator Enable. VGH_M is enabled when the voltage on this pin is more than 2.2 V. VGH_M goes to
GND when this pin is connected to GND.
5 VDD_1
Gate Pulse Modulator Low Voltage Input.
6 VDD_2
VCOM Amplifier Supply.
7 OUT
VCOM Amplifier Output.
8 NEG
Inverting Input of VCOM Amplifier.
9 POS
Noninverting Input of VCOM Amplifier.
10 AGND
Analog Ground.
11 ADJ
LDO Output Voltage Select. Refer to Table 13 for details.
12 LDO_OUT LDO Output.
13 VIN_1
Supply Input. This pin supplies power to the LDO and step-up switching regulator. Typically connected to VIN_2.
14 SS
Soft Start. A capacitor must be connected between GND and this pin to set the soft start time.
15 COMP
Compensation for the Step-Up Converter. A capacitor and resistor are connected in series between GND and this
pin for stable operation.
16 FREQ
Frequency Select. Set the switching frequency with a logic level. The step-up switching regulator operates at 650 kHz
when this pin is connected to GND and at 1.2 MHz when connected to VIN_1.
17 VIN_2
Step-Up Switching Regulator Power Supply. This pin supplies power to the driver for the switch. Typically
connected to VIN_1.
18 LX
Step-Up Switching Regulator Switch Node.
19 SHDN
Device Shutdown Pin. This pin allows users to shut the device off when connected to GND. The normal operating
mode is to pull this pin to VIN_1.
20 FB
Feedback Voltage Sense to Set the Output Voltage of the Step-Up Switching Regulator.
21 PGND
Step-Up Switching Regulator Power Ground.
22 CE
GPM Time Delay. A capacitor must be connected between GND and this pin to set the delay time.
23 RE
GPM Negative Ramp Rate. A resistor must be connected between GND and this pin to set the negative ramp rate.
24 VGH
Gate Pulse Modulator High Voltage Input.
Rev. 0 | Page 8 of 28







ADD8754 equivalent, schematic
VCOM AMPLIFIER
The output of the VCOM amplifier is designed to control the
voltage on the VCOM plane of the LCD display. The VCOM
amplifier is designed to source and sink the capacitive pulse
current and ensure stable operation with high load capacitance.
Input Overvoltage Protection
Whenever the input exceeds the supply voltage, attention must
be paid to the input overvoltage characteristics. When an
overvoltage occurs, the amplifier can be damaged, depending
on the voltage level and the magnitude of the fault current.
When the input voltage exceeds the supply voltage by more
than 0.6 V, the internal pin junctions allow current to flow from
the input to the supplies. This input current is not inherently
damaging to the device, provided it is 5 mA or less.
Short-Circuit Output Conditions
The VCOM amplifier does not have internal short-circuit protection
circuitry. As a precaution, do not short the output directly to the
positive power supply or to the ground.
GATE PULSE MODULATOR CIRCUIT
The gate pulse modulator is used for LCD applications in which
shaping of the gate high voltage signal improves image quality.
A charge pump is used to generate the on voltage, VGH. A lower
gate voltage level, VDD_1, is desired during the last portion of
the gate’s on time and is provided by VOUT. The integrated gate
pulse modulator circuit provides control over the slope and delay
of the transition between these two TFT on-voltage levels.
The gate pulse modulator circuit has four input pins (VGH,
VDD_1, VDPM, and VFLK) and one output pin (VGH_M).
VFLK is a digital control signal, usually provided by the timing
controller, whose high or low level determines which of the two
input voltages, VGH or VDD_1, is passed through to VGH_M.
The gate high modulator circuit becomes active when the voltage
on pin VDPM exceeds the turn-on threshold value of 2.2 V.
When the control voltage VFLK switches from logic low to logic
high during normal operation with VDPM at logic high (see
Figure 21), the output voltage VGH_M transitions from VDD_1
to VGH. When the control voltage VFK switches from logic
high to logic low, the output voltage VGH_M transitions from
VGH to VDD_1 after a time delay determined by the size of a
capacitor from the CE pin to the GND and a slew rate
determined by the size of resistor from the RE pin to the GND.
ADD8754
The delay capacitance in farad is calculated using the following
equation:
CE = (Delay Time) × 0.000238
The RE in ohms is calculated using the following equation:
( )RE = 302 5000
Slew Rate × Load Capacitance
When the voltage on the VDPM pin is less than the turn-on
threshold value, the CE pin is internally connected to GND to
discharge the delay capacitor.
VDPM
VFLK
GATE HIGH
VIN_1 MOD. CIRCUIT
L
O
G S3
I
C
GND
S1
S2
S4
GND
REF
VGH
VGH_M
CL
VDD_1
VOUT/VGH
DELAY CE
CAPACITOR
RAMP RE
RESISTOR
GND
Figure 20. Gate Pulse Modulator Functional Block Diagram
ENABLE – VDPM
LOW
CONTROL SIGNAL – VFLK
LOW
OUTPUT SIGNAL – VGH_M
WITH LOAD
CAPACITANCE CL
LOW
T1
T1
DELAY CONTROLLED
BY CE
SLOPE CONTROLLED BY RE
T2
VGH
VDD_1
T2
Figure 21. Gate Pulse Modulator Timing Diagram
Rev. 0 | Page 16 of 28










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