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PDF ( 数据手册 , 数据表 ) NB4L339

零件编号 NB4L339
描述 2.5 V / 3.3 V Differential 2:1 Clock IN to Differential LVPECL Clock Generator / Divider / Fan-Out Buffer
制造商 ON Semiconductor
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NB4L339 数据手册, 描述, 功能
NB4L339
2.5 V / 3.3 V Differential 2:1
Clock IN to Differential
LVPECL Clock Generator /
Divider / Fan-Out Buffer
MultiLevel Inputs w/ Internal Termination
Description
The NB4L339 is a multifunction Clock generator featuring a 2:1
Clock multiplexer front end and simultaneously outputs a selection of
four different divide ratios from its four divider blocks; ÷1/÷2/÷4/÷8.
One divide block has a choice of ÷1 or ÷ 2.
The output of each divider block is fannedout to two identical
differential LVPECL copies of the selected clock. All outputs provide
standard LVPECL voltage levels when externally terminated with a
50ohm resistor to VCC 2 V.
The differential Clock inputs incorporate internal 50W termination
resistors and will accept LVPECL, CML or LVDS logic levels.
The common Output Enable pin (EN) is synchronous so that the
internal dividers will only be enabled/disabled when the internal clock
is in the LOW state. This avoids any chance of generating a runt clock
pulse on the internal clock when the device is enabled/disabled as can
happen with an asynchronous control. An internal runt pulse could
lead to losing synchronization between the internal divider stages. The
internal enable flipflop is clocked on the falling edge of the input
clock. Therefore, all associated specification limits are referenced to
the negative edge of the clock input.
This device is housed in a 5x5 mm 32 pin QFN package.
Features
Maximum Input/Output Clock Frequency > 700 MHz
Low Skew LVPECL Outputs, 15 ps typical
1 ns Typical Propagation Delay
150 ps Typical Rise and Fall Times
0.15 ps Typical RMS Phase Jitter
0.5 ps Typical RMS Random Clock Period Jitter
LVPECL, CML or LVDS Input Compatible
Operating Range: VCC = 2.375 V to 3.6 V with VEE = 0 V
LVPECL Output Level; 750 mV PeaktoPeak, Typical
Internal 50W Input Termination Provided
Synchronous Output Enable/Disable
Asynchronous Master Reset
Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,
EP, and SG Devices
40°C to 85°C Ambient Operating Temperature
32Pin QFN, 5 mm x 5 mm
This is a PbFree Device
© Semiconductor Components Industries, LLC, 2012
September, 2012 Rev. 3
1
http://onsemi.com
MARKING
DIAGRAM
1 32
QFN32
MN SUFFIX
CASE 488AM
1
NB4L339
AWLYYWWG
G
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = PbFree Package
(Note: Microdot may be in either location)
Figure 1. Simplified Block Diagram
ORDERING INFORMATION
See detailed ordering and shipping information on page 11 of
this data sheet.
Publication Order Number:
NB4L339/D







NB4L339 pdf, 数据表
MR
CLK
Q (÷1)
Q (÷2)
Q (÷4)
Q (÷8)
NB4L339
Figure 6. Timing Diagram
CLK
MR
tRR
tRR
Q (÷n)
NOTE: On the rising edge of MR, Q goes HIGH after the first rising edge of CLK, following a hightolow clock transition.
Figure 7. Master Reset Timing Diagram
Internal Clock
Disabled
Internal Clock
Enabled
CLK
Q (÷n)
EN
Figure 8. Output Enable Timing Diagrams
The EN signal will “freeze” the internal divider flipflops
on the first falling edge of CLK after its assertion. The
internal divider flipflops will maintain their state during the
freeze. When EN is deasserted (LOW), and after the next
falling edge of CLK, then the internal divider flipflops will
“unfreeze” and continue to their next state count with proper
phase relationships.
http://onsemi.com
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