DataSheet8.cn


PDF ( 数据手册 , 数据表 ) AN-136

零件编号 AN-136
描述 A NEW GENERATION
制造商 Integrated Device Technology
LOGO Integrated Device Technology LOGO 


1 Page

No Preview Available !

AN-136 数据手册, 描述, 功能
www.DataSheet4U.com
Integrated Device Technology, Inc.
A NEW GENERATION OF
TAG SRAMS—THE IDT71215 AND
IDT71216
By Kelly Maas
APPLICATION
NOTE
AN-136
INTRODUCTION
The 71215 and 71216 represent a new generation of
integrated Tag SRAMs. Just as earlier Tag SRAMs such as
the 71B74 were better suited for tag applications than conven-
tional SRAMs, the 71215/16 go a step further by integrating
new features to significantly ease the design of high perfor-
mance cache subsystems for today’s high speed processors.
These Tag RAMs are designed for easy interfacing to Intel and
PowerPC processors, but are very flexible and can easily be
used in other applications as well.
This application note first provides some background infor-
mation on caches, then describes in detail the architecture
and operation of the 71215 and 71216. This is followed by
three application examples, then a brief discussion of cache
coherency protocol implementation using these Tag RAMs.
Since the 71215 and 71216 are very similar, the descriptions
and explanations in this application note apply to both unless
otherwise noted.
CACHE AND TAG BASICS
For those new to caches, a brief review of cache basics may
be worthwhile. A cache is a memory that provides a CPU with
high speed access to a subset of the data from main memory.
Our discussions are focused on the secondary cache, which
is also known as the L2 cache, but it is not much different from
the faster primary (L1) cache residing inside most CPUs.
The cache consists of a controller, a data memory and a tag
memory. The purpose of the data memory is to store the
active data from main memory, and is composed of either
synchronous burst or asynchronous SRAMs. The tag memory
stores indexes (part of the CPU address field) that indicate
which data is stored in the cache. Additionally, most caches
also require at least one bit of memory for each cache entry,
to indicate the valid or dirty status of that entry. Figure 1 shows
how the CPU address field relates to the cache and the tag
memory. This example includes valid and dirty status bits, and
represents a 512KB cache, 2GB cacheable address space,
32-byte line size, and 8-byte word size.
A31
MSB
A30
A19 A18
TAG MEMORY
12 1
1
TAG
LINE
VALID
LINE
DIRTY
DATA SRAM ADDRESS
A5 A4
A3
LSB
TAG
ADDRESS
COMPARATOR
MATCH
to CACHE CONTROLLER
3176 drw 01
Figure 1. CPU Address Field and the L2 Cache (Showing 512 KB cache size and 2 GB cacheable main memory)
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
PowerPC is a trademark of International Business Machines Corporation
Pentium is a trademark of Intel Corporation
©1995 Integrated Device Technology, Inc.
1/95







AN-136 pdf, 数据表
A NEW GENERATION OF TAG SRAMS—THE IDT71215 AND IDT71216
APPLICATION NOTE AN-136
will ripple through to BRDY /TA ), or if data SRAM accesses
require wait states (it’s necessary to toggle BRDY /TA from
cycle to cycle). For those times when neither device is driving
BRDY /TA , a pull-up resistor is used to keep the signal high. In
this case, it’s suggested that the controller drive BRDY /TA
high before putting it in a high impedance state. Thus, the
resistor is never used to generate a low to high transition and
therefore can be weak (3 Kto 20 K). Also, both the 71215/
16 and controller can remain off the BRDY /TA bus for ex-
tended periods of time if so desired. With this approach,
BRDYIN or TAIN (Burst Ready Input, Transfer Acknowledge
Input) is tied high.
66MHz
PENTIUM
A(5:30)
71215 TAG
CHIP SET
A(0:13)
TAG(0:11)
MATCH
STATUS BITS
BRDYH
BRDY BRDYOE
BRDYH
BRDYOE
BRDY
BRDY
The BRDY sources are totem-pole, NOT open-drain
3176 drw 09
Figure 9. Combining BRDY/TA : Bussing Option
REDUCED POWER
For the increasing number of applications that require a low
power standby mode, the 71215/16 includes an asynchro-
nous power down pin (PWRDN ). When it is driven low, both
the tag and status memories are shut down to save consider-
ably on power consumption. For optimum power savings, all
input and bidirectional signals should also be held at CMOS
voltage levels (near VCC or VSS). During power down, all
outputs are placed in a high impedance state and all data is
retained. All writes should be allowed to complete before
PWRDN is asserted. There is no minimum time that it must be
low. When exiting the power down state, there is only a very
short delay after the rising edge of PWRDN before normal
activity can be resumed.
SYSTEM USAGE
For applications not using the entire 12-bit tag field, the
unused TAG I/O pins should be pulled either high or low
through 1 Kto 5 Kresistors. For applications not using the
entire 3-bit status field, the unused inputs may be tied directly
to VCC or VSS, and the unused outputs are left unconnected.
All other unused inputs should be tied either to VCC or VSS as
appropriate for their function. This includes unused address
signals ift only part of the depth of the 71215/16 is used.
The second approach is to have the cache/memory con-
troller drive it’s BRDY /TA output into the BRDYIN /TAIN input
on the 71215/16 at all times. Inside the 71215/16, BRDYIN /
TAIN is registered by the clock then ANDed (negative logic
ORed) with the internally generated BRDY /TA . For this
approach, BRDYOE /TAOE is tied permanently low. The
controller no longer generates BRDYOE /TAOE , but instead
must generate BRDY /TA one cycle earlier because it is
delayed by one cycle in reaching the CPU. Note that BRDYH /
TAH only enables or disables the BRDY /TA generated inside
the 71215/16, and does not affect the propagation of BRDYIN/
TAIN through to the BRDY /TA output. Figure 10 shows this
approach for the 71215 and Pentium.
66MHz
PENTIUM
A(5:30)
71215 TAG
A(0:13)
TAG(0:11)
CHIP SET
MATCH
STATUS BITS
BRDY
BRDYH
BRDY BRDYIN
BRDYH
BRDY
BRDYIN is registered 3176 drw 10
Figure 10. Combining BRDY/TA : Pass-Through Option
BRDY /TA functions similar to MATCH (but opposite in
polarity) when the 71215/16 is not in match mode. It is high
impedance when the chip is deselected (or BRDYOE /TAOE is
high), and otherwise is driven high when out of match mode.
8














页数 12 页
下载[ AN-136.PDF 数据手册 ]


分享链接

Link :

推荐数据表

零件编号描述制造商
AN-136A NEW GENERATIONIntegrated Device Technology
Integrated Device Technology

零件编号描述制造商
STK15C88256-Kbit (32 K x 8) PowerStore nvSRAMCypress Semiconductor
Cypress Semiconductor
NJM4556DUAL HIGH CURRENT OPERATIONAL AMPLIFIERNew Japan Radio
New Japan Radio
EL1118-G5 PIN LONG CREEPAGE SOP PHOTOTRANSISTOR PHOTOCOUPLEREverlight
Everlight


DataSheet8.cn    |   2020   |  联系我们   |   搜索  |  Simemap