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PDF ( 数据手册 , 数据表 ) ADM1178

零件编号 ADM1178
描述 Hot Swap Controller and Digital Power Monitor
制造商 Analog Devices
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ADM1178 数据手册, 描述, 功能
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Hot Swap Controller and
Digital Power Monitor with ALERTB Output
ADM1178
FEATURES
Allows safe board insertion and removal from a live
backplane
Controls supply voltages from 3.15 V to 16.5 V
Precision current sense amplifier
Precision voltage input
12-bit ADC for current and voltage readback
Charge pumped gate drive for external N-channel FET
Adjustable analog current limit with circuit breaker
±3% accurate hot swap current limit level
Fast response limits peak fault current
Automatic retry or latch-off on current fault
Programmable hot swap timing via TIMER pin
Active-high ON pin
ALERTB output for overcurrent interrupt
I2C® fast mode-compliant interface (400 kHz maximum)
10-lead MSOP
APPLICATIONS
Power monitoring/power budgeting
Central office equipment
Telecommunication and data communication equipment
PCs/servers
GENERAL DESCRIPTION
The ADM1178 is an integrated hot swap controller and current
sense amplifier that offers digital current and voltage monitoring
via an on-chip, 12-bit analog-to-digital converter (ADC),
communicated through an I2C interface.
An internal current sense amplifier senses voltage across the sense
resistor in the power path via the VCC pin and the SENSE pin.
The ADM1178 limits the current through this resistor by control-
ling the gate voltage of an external N-channel FET in the power
path, via the GATE pin. The sense voltage (and, therefore, the
inrush current) is kept below a preset maximum.
The ADM1178 protects the external FET by limiting the time
that it spends with the maximum current running in it. This
current limit period is set by the choice of capacitor attached
to the TIMER pin. Additionally, the device provides protection
from overcurrent events that may occur after the hot swap event
is complete. In case of a short-circuit event, the current in the
sense resistor exceeds an overcurrent trip threshold, and the
FET is switched off immediately by pulling down the GATE pin.
FUNCTIONAL BLOCK DIAGRAM
ADM1178
VCC
SENSE
MUX
V
0
I
A1
12-BIT
SDA
ADC
I2C SCL
ADR
CURRENT
SENSE
AMPLIFIER
ALERT
ALERTB
ON
1.3V
UV COMPARATOR
GND
FET DRIVE
CONTROLLER
TIMER
Figure 1.
GATE
3.15V TO 16.5V
RSENSE N-CHANNEL FET
VCC SENSE
GATE
ADM1178
ON SDA
SCL
ALERTB
TIMER
GND ADR
CONTROLLER
P = VI
SDA
SCL
INTERRUPT
Figure 2. Applications Diagram
A 12-bit ADC can measure the current seen in the sense
resistor, as well as the supply voltage on the VCC pin. An alert
output can be set to trigger when the ADC current reading
exceeds a programmed overcurrent limit threshold.
An industry-standard I2C interface allows a controller to read
current and voltage data from the ADC. Measurements can be
initiated by an I2C command. Alternatively, the ADC can run
continuously, and the user can read the latest conversion data
whenever it is required. Up to four unique I2C addresses can be
created, depending on the way the ADR pin is connected.
The ADM1178 is packaged in a 10-lead MSOP.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
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ADM1178 pdf, 数据表
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ADM1178
TYPICAL PERFORMANCE CHARACTERISTICS
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0 2 4 6 8 10 12 14 16 18
VCC (V)
Figure 4. Supply Current vs. Supply Voltage
12
10
8
6
4
2
0
0 2 4 6 8 10 12 14 16
VCC (V)
Figure 5. Drive Voltage (VGATE − VCC) vs. Supply Voltage
18
0
–2
–4
–6
–8
–10
–12
–14
0 2 4 6 8 10 12 14 16
VCC (V)
Figure 6. Gate Pull-Up Current vs. Supply Voltage
18
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–40 –20
0 20 40
TEMPERATURE (°C)
60
80
Figure 7. Supply Current vs. Temperature (Gate On)
12
5V VIN
10
8
3.15V VIN
6
4
2
0
–40 –20
0 20 40
TEMPERATURE (°C)
60
80
Figure 8. Drive Voltage (VGATE − VCC) vs. Temperature
0
–2
–4
–6
–8
–10
–12
–14
–40
–20
0 20 40
TEMPERATURE (°C)
60
Figure 9. Gate Pull-Up Current vs. Temperature
80
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ADM1178 equivalent, schematic
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ADM1178
VOLTAGE AND CURRENT READBACK
In addition to providing hot swap functionality, the ADM1178
also contains the components to allow voltage and current
readback over an Inter-IC (I2C) bus. The voltage output of the
current sense amplifier and the voltage on the VCC pin are fed
into a 12-bit ADC via a multiplexer. The device can be instructed
to convert voltage and/or current at any time during operation
via an I2C command. When all conversions are complete, the
voltage and/or current values can be read out to 12-bit accuracy
in two or three bytes.
SERIAL BUS INTERFACE
Control of the ADM1178 is carried out via the I2C bus. This
interface is compatible with I2C fast mode (400 kHz maximum).
The ADM1178 is connected to this bus as a slave device, under
the control of a master device.
IDENTIFYING THE ADM1178 ON THE I2C BUS
The ADM1178 has a 7-bit serial bus slave address. When the
device powers up, it does so with a default serial bus address.
The three MSBs of the address are set to 111, and the two MSBs
are set to 10, giving an address of 111x10. Bit A2 and Bit A3 are
determined by the state of the ADR pin. There are four different
configurations available on the ADR pin that correspond to
four different I2C addresses for these bits (see Table 5). This
scheme allows four ADM1178 devices to operate on a single
I2C bus.
Table 5. Setting I2C Addresses via the ADR Pin
ADR Configuration
Address
Low state
0xE4
Resistor to GND
0xEC
Floating (unconnected)
0xF4
High state
0xFC
GENERAL I2C TIMING
Figure 35 and Figure 36 show timing diagrams for general read
and write operations using the I2C. The I2C specification defines
conditions for different types of read and write operations, which
are discussed later. The general I2C protocol operates as follows:
1. The master initiates data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data line, SDA, while the serial clock line, SCL, remains
high. This indicates that a data stream follows.
All slave peripherals connected to the serial bus respond to
the start condition and shift in the next eight bits, consisting
of a 7-bit slave address (MSB first), plus an R/W bit that
determines the direction of the data transfer; that is,
whether data is written to or read from the slave device (0
= write, 1 = read).
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the
low period before the ninth clock pulse, known as the
acknowledge bit, and holding it low during the high period
of this clock pulse. All other devices on the bus remain
idle, while the selected device waits for data to be read
from it or written to it. If the R/W bit is 0, the master
writes to the slave device. If the R/W bit is 1, the master
reads from the slave device.
2. Data is sent over the serial bus in sequences of nine clock
pulses: eight bits of data followed by an acknowledge bit
from the slave device. Data transitions on the data line
must occur during the low period of the clock signal and
remain stable during the high period because a low-to-
high transition when the clock is high can be interpreted as
a stop signal.
If the operation is a write operation, the first data byte after
the slave address is a command byte. This tells the slave
device what to expect next. It can be an instruction, such
as telling the slave device to expect a block write; or it can
be a register address that tells the slave where subsequent
data is to be written.
Because data can flow in only one direction, as defined by
the R/W bit, it is not possible to send a command to a slave
device during a read operation. Before doing a read operation,
it may first be necessary to do a write operation to tell the
slave what sort of read operation to expect and/or the
address from which data is to be read.
3. When all data bytes have been read or written, stop
conditions are established. In write mode, the master pulls
the data line high during the 10th clock pulse to assert
a stop condition. In read mode, the master device releases
the SDA line during the low period before the ninth clock
pulse, but the slave device does not pull it low. This is known as
a no acknowledge. The master then takes the data line low
during the low period before the 10th clock pulse, then high
during the 10th clock pulse to assert a stop condition.
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