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PDF ( 数据手册 , 数据表 ) ADM1175

零件编号 ADM1175
描述 Hot Swap Controller and Digital Power Monitor
制造商 Analog Devices
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ADM1175 数据手册, 描述, 功能
Data Sheet
Hot Swap Controller and
Digital Power Monitor with Convert Pin
ADM1175
FEATURES
Allows safe board insertion and removal from
a live backplane
Controls supply voltages from 3.15 V to 16.5 V
Precision current sense amplifier
Precision voltage input
12-bit ADC for current and voltage readback
Charge pumped gate drive for external N-channel FET
Adjustable analog current limit with circuit breaker
±3% accurate hot swap current limit level
Fast response limits peak fault current
Automatic retry or latch-off on current fault
Programmable hot swap timing via TIMER pin
Active high and active low ON/ONB pin options
Convert start pin (CONV)
I2C fast mode-compliant interface (400 kHz maximum)
10-lead MSOP
APPLICATIONS
Power monitoring/power budgeting
Central office equipment
Telecommunications and data communications equipment
PCs/servers
GENERAL DESCRIPTION
The ADM1175 is an integrated hot swap controller and current
sense amplifier that offers digital current and voltage monitoring
via an on-chip, 12-bit analog-to-digital converter (ADC),
communicated through an I2C® interface.
An internal current sense amplifier measures voltage across
the sense resistor in the power path via the VCC pin and the
SENSE pin.
The ADM1175 limits the current through this resistor by
controlling the gate voltage (via the GATE pin) of an external
N-channel FET in the power path. The voltage across the sense
resistor (and, therefore, the inrush current) is kept below a
preset maximum.
The ADM1175 protects the external FET by limiting the time
that the maximum current runs through it. This current limit
period is set by the value of the capacitor attached to the TIMER
pin. Additionally, the device provides protection from overcurrent
events that may occur once the hot swap event is complete. In
the case of a short-circuit event, the current in the sense resistor
exceeds an overcurrent trip threshold, and the FET is switched
off immediately by pulling down the GATE pin.
FUNCTIONAL BLOCK DIAGRAM
ADM1175-1
MUX
CONV
VCC
V
0
SENSE
I
A1
12-BIT
SDA
ADC
I2C SCL
ADR
CURRENT
SENSE
AMPLIFIER
ON
1.3V
UV COMPARATOR
GND
FET DRIVE
CONTROLLER
TIMER
Figure 1.
GATE
3.15V TO 16.5V
RSENSE N-CHANNEL FET
VCC SENSE
GATE
ADM1175-1
ON SDA
SCL
CONV
TIMER
GND ADR
CONTROLLER
P = VI
SDA
SCL
CONV
Figure 2. Applications Diagram
A 12-bit ADC can measure the current seen in the sense resistor,
as well as the supply voltage on the VCC pin. An industry-standard
I2C interface allows a controller to read current and voltage data
from the ADC. Measurements can be initiated by an I2C command
or via the convert (CONV) pin. The CONV pin is especially
useful for synchronizing reads on multiple ADM1175 devices.
Alternatively, the ADC can run continuously, and the user can
read the latest conversion data whenever it is required. Up to four
unique I2C addresses can be created, depending on how the ADR
pin is connected.
The ADM1175 is packaged in a 10-lead MSOP.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006–2012 Analog Devices, Inc. All rights reserved.







ADM1175 pdf, 数据表
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0 2 4 6 8 10 12 14 16 18
VCC (V)
Figure 4. Supply Current vs. Supply Voltage
12
10
8
6
4
2
0
0 2 4 6 8 10 12 14 16
VCC (V)
Figure 5. Drive Voltage (VGATE − VCC) vs. Supply Voltage
18
0
–2
–4
–6
–8
–10
–12
–14
0 2 4 6 8 10 12 14 16
VCC (V)
Figure 6. Gate Pull-Up Current vs. Supply Voltage
18
ADM1175
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–40 –20
0 20 40
TEMPERATURE (°C)
60
80
Figure 7. Supply Current vs. Temperature (Gate On)
12
5V VCC
10
8
3.15V VCC
6
4
2
0
–40 –20
0
20 40 60 80
TEMPERATURE (°C)
Figure 8. Drive Voltage (VGATE − VCC) vs. Temperature
0
–2
–4
–6
–8
–10
–12
–14
–40
–20
0
20 40 60
TEMPERATURE (°C)
Figure 9. Gate Pull-Up Current vs. Temperature
80
Rev. C | Page 7 of 24







ADM1175 equivalent, schematic
Data Sheet
ADM1175
VOLTAGE AND CURRENT READBACK
In addition to providing hot swap functionality, the ADM1175
also contains the components to allow voltage and current
readback over an I2C bus. The voltage output of the current
sense amplifier and the voltage on the VCC pin are fed into a
12-bit ADC via a multiplexer. The device can be instructed to
convert voltage and/or current at any time during operation via
an I2C command or an assertion on the convert start (CONV)
pin. When all conversions are complete, the voltage and/or current
values can be read back with 12-bit accuracy in two or three bytes.
SERIAL BUS INTERFACE
Control of the ADM1175 is carried out via the I2C bus. This
interface is compatible with I2C fast mode (400 kHz maximum).
The ADM1175 is connected to this bus as a slave device, under
the control of a master device.
IDENTIFYING THE ADM1175 ON THE I2C BUS
The ADM1175 has a 7-bit serial bus slave address. When the
device powers up, it does so with a default serial bus address. The
five MSBs of the address are set to 11010; the two LSBs are deter-
mined by the state of the ADR pin. There are four different
configurations available on the ADR pin that correspond to four
different I2C addresses for the two LSBs (see Table 5). This scheme
allows four ADM1175 devices to operate on a single I2C bus.
GENERAL I2C TIMING
Figure 32 and Figure 33 show timing diagrams for general write
and read operations using the I2C. The I2C specification defines
conditions for different types of read and write operations, which
are discussed in the Write and Read Operations section. The
general I2C protocol operates as follows:
1. The master initiates data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data line, SDA, while the serial clock line, SCL, remains
high. This indicates that a data stream is to follow. All slave
peripherals connected to the serial bus respond to the start
condition and shift in the next eight bits, consisting of a 7-bit
slave address (MSB first), plus an R/W bit that determines
the direction of the data transfer, that is, whether data is
written to or read from the slave device (0 = write,
1 = read).
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the
low period before the ninth clock pulse, known as the
acknowledge bit, and holding it low during the high period
of this clock pulse. All other devices on the bus remain idle,
while the selected device waits for data to be read from it
or written to it. If the R/W bit is 0, the master writes to the
slave device. If the R/W bit is 1, the master reads from the
slave device.
2. Data is sent over the serial bus in sequences of nine clock
pulses: eight bits of data followed by an acknowledge bit
from the slave device. Data transitions on the data line
must occur during the low period of the clock signal and
remain stable during the high period, because a low-to-
high transition when the clock is high can be interpreted as
a stop signal.
If the operation is a write operation, the first data byte after
the slave address is a command byte. This tells the slave
device what to expect next. It can be an instruction, such as
telling the slave device to expect a block write; or it can be
a register address that tells the slave where subsequent data
is to be written.
Because data can flow in only one direction, as defined by
the R/W bit, it is not possible to send a command to a slave
device during a read operation. Before performing a read
operation, it may be necessary to first execute a write
operation to tell the slave what sort of read operation to
expect and/or the address from which data is to be read.
3. When all data bytes are read or written, stop conditions are
established. In write mode, the master pulls the data line
high during the 10th clock pulse to assert a stop condition.
In read mode, the master device releases the SDA line
during the SCL low period before the ninth clock pulse,
but the slave device does not pull it low. This is known as a
no acknowledge. The master then takes the data line low
during the SCL low period before the 10th clock pulse, then
high during the 10th clock pulse to assert a stop condition.
Table 5. Setting I2C Addresses via the ADR Pin
Base Address
ADR Pin State
11010
Ground
Resistor to ground
Floating
High
ADR Pin Logic State
00
01
10
11
Address in Binary1
1101000X
1101001X
1101010X
1101011X
Address in Hex
0xD0
0xD2
0xD4
0xD6
1 X = don’t care.
Rev. C | Page 15 of 24










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