DataSheet8.cn


PDF ( 数据手册 , 数据表 ) OXCF950

零件编号 OXCF950
描述 Single full-duplex asynchronous channel 128-byte deep transmitter / receiver FIFO
制造商 Oxford Semiconductor
LOGO Oxford Semiconductor LOGO 


1 Page

No Preview Available !

OXCF950 数据手册, 描述, 功能
www.DataSheet4U.com
FEATURES
Single full-duplex asynchronous channel
128-byte deep transmitter / receiver FIFO
Fully software compatible with industry standard
16C550 type UARTs
Readable FIFO levels
System clock up to 60MHz
Flexible clock prescaler from 1 to 31.875
9-bitdata framing as well as 5,6,7 and 8
Detection of bad data in the receiver FIFO
Automated in-band flow control using programmable
Xon/Xoff characters
Transmitter and receiver can be disabled
Low power CMOS
3.3V operation, 5V tolerant I/O
Extended temperature range –40C to +105C
Software compatible with OXCF950
16C950 mode for local bus applications
Generic embedded driver compatibility mode
OXCF950 rev B
DATA SHEET V1.0
Programmable by external MicrowireTM EEPROM
(EEPROM programmed via Oxford Semiconductor
utilities).
Extremely low power consumption by use of
asynchronous UART core and power down (sleep)
modes
Range of packages -Ultra small 48 pin TQFP package
or a 48 ball TFBGA.
Supports all UART types 450 up to 950 (fully
programmable)
CF+ Compliant (Revision 1.4).
16-bit PC Card Compliant (PCMCIA Revision 7.1)
8 bit Local Bus interface included for PCMCIA
applications
2 Multi-purpose I/O pins which can be configured as
interrupt inputs
DESCRIPTION
The OXCF950 rev B is a low cost asynchronous 16-bit PC
card (henceforth referred to as PCMCIA) or Compact Flash
(henceforth referred to as CF) UART (and Local Bus)
device. Local Bus Selection is performed by use of a
MODE pin. Note that Local Bus mode uses indirect
addressing, which is only supported by PCMCIA.
The 3.3V technology has been specified to operate as low
as 2.7 V to allow an in-line regulator to be used for mixed
3V/5V applications. All the I/Os are 5V tolerant with the
exception of the clock/crystal oscillator input.
The EEPROM interface allows the programming of the
Attribute Memory, UART and Local Configuration Registers
during power up or hard/soft reset. This allows different
card manufacturers to modify the information contained in
the Attribute memory or UART/registers as required, for
example PC-Card ID value.
A number of power -down modes are included to keep
power consumption to a minimum. Such features include
clock division (fully programmable) and sleep modes when
a function of the OXCF950 rev B is not being used.
Oxford Semiconductor Ltd.
25 Milton Park, Abingdon, Oxon, OX14 4SH, UK
Tel: +44 (0)1235 824900
The OXCF950 rev B contains a single-channel ultra-high
performance UART offering data rates up to 15Mbps and
128-deep transmitter and receiver FIFOs. Deep FIFOs
reduce CPU overhead and allow utilisation of higher data
rates.
It is software compatible with the widely used industry-
standard 16C550 ty pe devices and compatibles, as well as
other OX16C95x family devices.
In addition to increased performance and FIFO size, the
OXCF950 rev B also provides enhanced features including
improved flow control. Automated software flow control
using Xon/Xoff and automated hardware flow control using
CTS#/RTS# and DSR#/DTR# prevent FIFO over-run. Flow
control and interrupt thresholds are fully programmable and
readable, enabling programmers to fine- tune the
performance of their system. FIFO levels are readable to
facilitate fast driver applications.
The addition of software reset enables recovery from
unforeseen error conditions allowing drivers to restart
gracefully. The OXCF950 rev B supports 9-bit data frames
used in multi-drop industrial protocols. It also offers multiple
© Oxford Semiconductor 2001 .
OXCF950B DATA SHEET REV 1.0 –July 2002
Part No. OXCF950-TQ-B







OXCF950 pdf, 数据表
OXFORD SEMICONDUCTOR LTD.
3 PIN DESCRIPTIONS
OXCF950 rev B DATA SHEET V 1.0
TQFP Pin Number (TFBGA ball) Dir1
CF/PCMCIA Interface and Control
46, 45, 43, 42
I
(D4, A2, A3, B3)
6, 7, 10, 11, 12, 37, 38, 41
I/O
(E2, E1, F1, F3, G1, A6, B5, A4)
44 (C3)
IU
5 (D1)
IU
4 (D2)
I
1 (B1)
I
3 (C1)
2 (C2)
32 (C5)
IU
IU
O
O
47 (B2)
48 (A1)
O
IU
O
UART / Local Bus Function
24 (H6)
O
23 (G5)
I
29 (E6)
26 (F5)
I
O
Name
A[3:0]
D[7:0]
REG#
CE[1]#
OE#
WE#
IORD#
IOWR#
WP
IOIS16#
INT
RESET
READY#
IREQ#
SOUT
IrDA_Out
SIN
IrDA_In
DCD#
DTR#
485_En
25 (G6)
27 (F6)
Tx_Clk_Out
O RTS#
I CTS#
Description
PCMCIA/CF address bus, bits [3:0]
PCMCIA/CF data bi-directional bus.
Register select and I/O enable
Active low card enable
Active low memory read enable
Active-low write enable used for strobing Memory Write data
(Attribute memory).
Active-low I/O read enable
Active-low I/O write enable
Write protect (in Memory only mode)
Data is 16 bit (in IO and Memory mode)
C950 Mode:Active-high interrupt request
PCMCIA/CF Reset
Device ready (in Memory only mode)
Active-low Interrupt request (in C950, IO and Memory mode).
UART serial data output.
UART IrDA data output when MCR[6] is set in enhanced
mode.
UART serial data input.
UART IrDA data input when IrDA mode is enabled (see
above).
Active-low modem data-carrier-detect input.
Active-low modem data- terminal-ready output. If automated
DTR# flow control is enabled, the DTR# pin is asserted and
de-asserted if the receiver FIFO reaches or falls below the
programmed thresholds, respectively.
In RS485 half-duplex mode, the DTR# pin may be
programmed to reflect the state of the transmitter empty bit to
automatically control the direction of the RS485 transceiver
buffer (see register ACR[4:3]).
Transmitter 1x clock (baud rate generator output). For
isochronous applications, the 1x (or Nx) transmitter clock may
be asserted on the DTR# pin (see register CKS[5:4]).
Active–low modem request- to-send output. If automated
RTS# flow control is enabled, the RTS# pin is de-asserted
and reasserted whenever the receiver FIFO reaches or falls
below the programmed thresholds, respectively.
Active-low modem clear-to-send input. If automated CTS#
flow control is enabled, upon de-assertion of the CTS# pin,
the transmitter will complete th e current character aPnadgeen8ter







OXCF950 equivalent, schematic
OXFORD SEMICONDUCTOR LTD.
OXCF950 rev B DATA SHEET V 1.0
Each of the local configuration registers are explained in the following sections. The offsets assume normal or local bus mode,
and these are the offsets that should be used when accessing the registers via the EEPROM.
EEPROM Status and Control register ‘ESC’(Offset 0x08)
This register defines the control on the serial EEPROM. The individual bits are described in Table 7.
Bits Description
Read/Write
Reset
EEPROM PCMCIA
7:6 Reserved
- R 000
5 EEPROM Overrun.
- R0
Set when an invalid EEPROM image causes the end of the EEPROM to be
read before the end of the programming sequence. In this state the
OXCF950 is set as though no EEPROM is attached.
This feature is new to OXCF950 rev B
4 EEPROM Data In.
- RX
For reads from the EEPROM this input bit is the output-data (DO) of the
external EEPROM connected to EE_DI pin
3 EEPROM Data Out.
- R/W 0
For writes to the EEPROM, this output bit feeds the inpu-tdata of the
external EEPROM (DI). This bit is output on the devices EE_DO and
clocked into the EEPROM by EE_CK
2 EEPROM Clock.
- R/W 0
For reads or writes to the external EEPROM toggle this bit to generate an
EEPROM clock (EE_CK pin)
1 EEPROM Chip Select.
- R/W 0
When ‘1’ the EEPROM chip select pin EE_CS is activated (high). When ‘0’
EE_CS is de-activated (low)
0 EEPROM Valid
A ‘1’ indicates that a valid EEPROM program header is present
- RX
Table 7: EEPROM Status and Control Register
Multi-Purpose I/O Configuration register ‘MIC’ (Offset 0x09)
This register configures the operation for the multi-purpose I/O pins ‘MIO[1:0]’ as follows
Bits Description
7:4 Reserved
3:2 MIO1 Configuration register
00 -> MIO1 is a non-inverting input pin
01 -> MIO1 is an inverting input pin
10 -> MIO1 is an output pin driving ‘0’
11 -> MIO1 is an output pin driving ‘1’
1:0 MIO0 Configuration register
00 -> MIO0 is a non-inverting input pin
01 -> MIO0 is an inverting input pin
10 -> MIO0 is an output pin driving ‘0’
11 -> MIO0 is an output pin driving ‘1’
Read/Write
EEPROM PCMCIA
-R
W R/W
Reset
0000
00
W R/W 00
Table 8: Multi Purpose I/O Configuration Register
Page 16










页数 30 页
下载[ OXCF950.PDF 数据手册 ]


分享链接

Link :

推荐数据表

零件编号描述制造商
OXCF950Single full-duplex asynchronous channel 128-byte deep transmitter / receiver FIFOOxford Semiconductor
Oxford Semiconductor

零件编号描述制造商
STK15C88256-Kbit (32 K x 8) PowerStore nvSRAMCypress Semiconductor
Cypress Semiconductor
NJM4556DUAL HIGH CURRENT OPERATIONAL AMPLIFIERNew Japan Radio
New Japan Radio
EL1118-G5 PIN LONG CREEPAGE SOP PHOTOTRANSISTOR PHOTOCOUPLEREverlight
Everlight


DataSheet8.cn    |   2020   |  联系我们   |   搜索  |  Simemap