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PDF ( 数据手册 , 数据表 ) OX16PCI952

零件编号 OX16PCI952
描述 Integrated High Performance Dual UARTs
制造商 Oxford Semiconductor
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OX16PCI952 数据手册, 描述, 功能
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FEATURES
OX16PCI952 DATA SHEET
Integrated High Performance Dual UARTs,
Parallel Port and 5.0v PCI interface
DS_B008A_00
Two 16C950 High performance UART channels
IEEE1284 Compliant SPP/EPP/ECP parallel port
Multi- function target PCI controller. Fully compliant to
PCI bus specification 2.2 and PCI Power Management
1.0.
Function access to pre-configure each UART and the
parallel port, prior to handover to generic device
drivers.
UARTs fully software compatible with 16C550- type
devices.
Baud rates up to 15Mbps in asynchronous mode and
60Mbps in external 1x clock mode
128-byte deep FIFO per transmitter and receiver
Flexible clock prescaler from 1 to 31.875
Automated in-band flow control using programmable
Xon/Xoff in both directions
DESCRIPTION
Automated out-of-band flow control using CTS#/RTS#
and/or DSR#/DTR#
Arbitrary trigger levels for receiver and transmitter
FIFO interrupts and automatic in-band and out-of-
band flow control
Infra-red (IrDA) receiver and transmitter operation
5, 6, 7, 8 and 9-bits data framing
Global Interrupt Status and readable FIFO levels to
facilitate implementation of efficient device drivers
Detection of bad data in the receiver FIFO
2 multi-purpose IO pins which can be configured as
interrupt inputs or ‘wake-up’ pins (via local registers).
Auto-detection of a range of optional MicrowireTM
compatible EEPROMs, to reconfigure device.
Operation via IO or memory mapping.
5.0V operation
128 pin TQFP package
The OX16PCI952 is a single chip solution for PCI-based
serial and parallel expansion add-in cards. It is a dual
function device, offering IO or memory mapped access to
the two ultra-high performance OX16C950 UARTs and the
bi-directional parallel port. These functions are defined by
Function 0 and Function 1, respectively. Serial port cards
with 2 serial ports and a parallel port can be designed
without redefining any device parameters.
Each UART channel in the OX16PCI952, is the fastest
available PC-compatible UART, offering data rates up to
15Mbps and 128-byte deep transmitter and receiver FIFOs.
The deep FIFOs reduce CPU overhead and allow
utilisation of higher data rates. Each UART channel is
software compatible with the widely used industry-standard
16C550 devices and compatibles, as well as the
OX16C95x family of high performance UARTs. In addition
to increased performance and FIFO size, the UARTs also
provide the full set of OX16C95x enhanced features
including automated in-band flow control, readable FIFO
levels, etc.
The parallel port is an IEEE 1284 compliant SPP, EPP and
ECP parallel port that fully supports the existing Centronics
interface. For legacy applications, the PCI resources have
been arranged so that the parallel port can be located at
standard I/O addresses
Oxford Semiconductor Ltd.
25 Milton Park, Abingdon, Oxon, OX14 4SH, UK
Tel: +44 (0)1235 824900 Fax: +44(0)1235 821141
A set of local registers is available to enhance device driver
efficiency and reduce interrupt latency. Each internal UART
has features such as shadowed FIFO fill levels, an interrupt
source register and Good-Data Status, readable in
consecutive DWORD registers and is visible to logical
function0 in both IO space and memory space. The local
registers also provide additional controls for each UART
and the parallel port, to customise the device for the end-
users application.
The efficient 32-bit, 33MHz target-only interface is
compliant with the PCI bus specification version 2.2 and
version 1.0 of PCI Power Management Specification.
For full flexibility, all the default configuration register
values can be overwritten using an optional MicrowireTM
compatible serial EEPROM.
This EEPROM can also be used to provide function access
to pre-configure each UART into enhanced modes or pre-
configure the parallel port, prior to any PCI configuration
accesses and before control is handed to generic device
drivers.
MicrowireTM is a trade mark of National Semiconductor.
© Oxford Semiconductor 2001
OX16PCI952 Datasheet rev 1.1 – June 2001
Part No. OX16PCI952-TQFP- A







OX16PCI952 pdf, 数据表
OXFORD SEMICONDUCTOR LTD.
OX16PCI952
4 PIN DESCRIPTION
Please refer to Section “Pin Information” for actual Signal Name to Pin Number assignments.
Pins
PCI interface
2, 5, 6, 7, 8, 12, 13, 14, 15,
32, 33, 34, 35, 36, 39, 40, 41,
43, 44, 47, 48, 49, 50, 51, 52,
121, 122, 123, 124, 125, 126,
127
Dir1
P_I/O
Name
AD[31:0]
Description
Multiplexed PCI Address/Data bus
3, 16, 31, 42
117
17
24
18
23
25
28
27
26
4
115
113
114
120
Serial port pins
88
111
101
P_I
P_I
P_I
P_O
P_I
P_O
P_O
P_I/O
P_O
P_I/O
P_I
P_I
P_OD
P_OD
I
O
O
C/BE[3:0]#
PCI CLK
FRAME#
DEVSEL#
IRDY#
TRDY#
STOP#
PAR
SERR#
PERR#
IDSEL
RST#
INTA#,
INTB#
PME#
PCI Command/Byte enable
PCI system clock
Cycle Frame
Device Select
Initiator ready
Target ready
Target Stop request
Parity
System error
Parity error
Initialization device select
PCI system reset
PCI interrupts
Power management event
FIFOSEL
EXT_DATA_OUT[0]
EXT_DATA_OUT[1]
FIFO select.
For backward compatibility with 16C550, 16C650 and
16C750 devices the FIFO depth of both UARTs is 16 when
FIFOSEL is low. The FIFO size of both UARTs is increased
to 128 when FIFOSEL is high.
The FIFO size of each UART may also be set to 128 by
setting the UARTs FCR[5] when LCR[7] is set, or by putting
the device into enhanced mode.
The unlatched state of this pin is readable by software.
Serial data output, Uart 0
Serial data output, Uart 1.
111
O IrDA_Out[0]
UART IrDA data outputs, for UART 0 and 1.
101
O IrDA_Out[1]
Serial data output pins redefined as IrDA data outputs when
MCR[6] of the corresponding UART channel is set in
enhanced mode
104 I EXT_DATA_IN[0] Serial data input, UART 0.
94 I EXT_DATA_IN[1] Serial data input, UART 1.
104
I IrDA_In[0]
UART IrDA data inputs, for UART 0 and 1.
94
I IrDA_In[1]
Serial data input pins redefined as IrDA data inputs when
MCR[6] of the corresponding UART channel is set in
enhanced mode
DataSheet Revision 1.1
Page 8







OX16PCI952 equivalent, schematic
OXFORD SEMICONDUCTOR LTD.
OX16PCI952
Register name
Function 0
Dual UART
Reset value
Function 11
Parallel Port
Program read/write
EEPROM PCI
Vendor ID
Device ID
Command
Status
Revision ID
Class code
Header type
BAR 0
BAR 1
BAR 2
BAR 3
BAR 4
Subsystem VID
Subsystem ID
Cap ptr.
Interrupt line
Interrupt pin
Cap ID
Next ptr.
PM capabilities
PMC control/
status register
0x1415
0x9521
0x0000
0x0290
0x00
0x070006
0x80
0x00000001
0x00000001
0x00000001
0x00000000
0x00000000
0x1415
0x0001
0x40
0x00
0x012
0x01
0x00
0x6C01
0x0000
0x1415
0x9523
0x0000
0x0290
0x00
0x070101
0x80
0x00000001
0x00000001
0x00000001
0x00000000
-
0x1415
0x0001
0x40
0x00
0x012
0x01
0x00
0x6C01
0x0000
Table 5: PCI configuration space Reset Values
W
W
-
W (bit 4)
-
W
W (bit 7)
-
-
-
-
-
W
W
-
-
W
-
-
W
-
R
R
R/W
R/W
R
R
R
R/W
R/W
R/W
R/W
R/W
R
R
R
R/W
R
R
R
R
R/W
NOTE 1: Function 1 PCI Configuration Space is available only when the OX16PCI952 is operating in the dual-function device mode (MODE0 pin = ‘0’).
Configuration accesses to Function 1 in the single function device mode (MODE0 pin = ‘1’) will result in ‘Master-Aborts’.
NOTE 2 : Default Interrupt pins values for function 0 and function 1 result in both functions asserting interrupts on the pin INTA#. The default values can be re-
programmed by the serial controller so that the 2 functions can assert interrupts onto separate (function dependent) interrupt pins.
DataSheet Revision 1.1
Page 16










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