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PDF ( 数据手册 , 数据表 ) OX16PCI954

零件编号 OX16PCI954
描述 HIGH-PERFORMANCE UART FAMILY REFERENCE DRIVERS
制造商 Oxford Semiconductor
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OX16C95x
OX16PCI954
HIGH-PERFORMANCE UART FAMILY
REFERENCE DRIVERS
This document describes installation and use of the Oxford Semiconductor reference
drivers for the OX16C95x high performance UART family, including the OX16PCI954
Quad UART with PCI interface.
Version 2.0 (01 February 2000)







OX16PCI954 pdf, 数据表
Custom solutions & drivers for the OX16PCI954
VERSION 1.0
FIFOs
This page provides three device modes. 450 mode, which forces the UART to operate in byte mode (i.e with the FIFO disabled), 550 mode
which operates with 16 byte deep FIFOs, 550 trigger levels and driver generated flow control (non-automated). Finally, 950 mode, which
operates with full 128 byte FIFOs, fully adjustable trigger levels and automated flow-control.
The four sliders allow adjustment of the various trigger levels in 550 and 950 modes. These are described below:
Transmitter FIFO interrupt trigger level - When the level of data in the transmit FIFO falls below this value, a transmitter interrupt
is triggered. Setting this value to zero will not trigger an interrupt until the transmitter is completely idle. In 450 and 550 mode this
is fixed at 1.
Receiver FIFO interrupt trigger level - When the level of data in the receiver FIFO reaches this value, a receiver data interrupt is
triggered. In 450 mode this is fixed at 1, In 550 mode it can take 4 discrete values 1,4,8 & 14.
Flow On flow-control limit - When the level of data in the receiver FIFO reaches this value as data is read from the FIFO, a
handshake is triggered to instruct the remote transmitter that it is free to transmit data (E.g. Transmit an XON character to the
remote machine). In 450 and 550 mode this level is fixed at 1.
Flow Off flow-control limit - When the level of data in the receiver FIFO reaches this value as it fills up, a handshake is triggered to
instruct the remote transmitter to stop sending data as the FIFO is becoming full. (E.g. Transmit an XOFF character to the remote
machine). In 450 mode this level is fixed at 1, in 550 mode it assumes the same value as the receiver FIFO interrupt trigger level.
The FIFO trigger levels can be fine tuned to gain optimum performance, depending on system performance, baud rate used, levels of serial
traffic etc. The default Receiver FIFO trigger level is preset at a value of 64; this should be increased for higher performance, but in some
cases a high trigger level will result in the port not detecting PnP serial devices.
5.1.2 Windows 2000 configuration
Settings
This page contains the standard Baud rate / Data bits / Parity / Stop bits and Flow control options found on most COM port settings pages.
These settings modify the default settings used by Windows. Most applications that use COM ports will override these settings with their
own comms parameters.
This page also provides configurable RS485 half-duplex operation. RS232 applications will not use this, and the DTR pin should be
configured as ‘normal’. However if RS485 line drivers are used, the driver can configure the DTR pin to enable the transmitter, in active-high
or active-low form. Note: if RS422/485 line drivers are selected, the driver will not allow DTR/DSR flow control, as these pins are not defined
in RS422 protocols.
Data Rate
This page provides a list of common crystal values used with COM ports. Select “Detect crystal frequency” to detect the input clock
frequency to the UART. (This requires that the port is not currently in use by another application).
The baud rate can optionally be adjusted according to the data rate required. To enable the advanced baud rate configuration options,
deselect the “Use default baud rate” box. In normal operation, the driver will generate the desired baud rate from the crystal frequency. The
quad speed option will multiply all application selected baud rates by 4 by utilising the OX16C95x Times clock register (TCR). The driver
can multiply this baud rate, or divide it using the Clock Prescaler register (CPR).
The clock pre-divisor is used to divide the input clock prior to baud rate generation. This means a high speed crystal (E.g 50MHz) can be
pre-divided to generate standard baud rates (In this case 50 / 27.125 = 1.8433 MHz, which will emulate a 1.8432 MHz crystal with less than
0.01% bit rate error). Alternatively, the pre-divisor could be switched off to allow data rates up to 12.5Mbps to be generated.
Oxford Semiconductor Ltd.
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