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PDF ( 数据手册 , 数据表 ) T224160B

零件编号 T224160B
描述 256K x 16 DYNAMIC RAM FAST PAGE MODE
制造商 Taiwan Memory Technology
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T224160B 数据手册, 描述, 功能
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tm TE
CH
DRAM
T224160B
256K x 16 DYNAMIC RAM
FAST PAGE MODE
FEATURES
Industry-standard x 16 pinouts and timing
functions.
Single 5V (±10%) power supply.
All device pins are TTL- compatible.
512-cycle refresh in 8ms.
Refresh modes: RAS only, CAS BEFORE
RAS (CBR) and HIDDEN.
Conventional FAST PAGE MODE access cycle.
BYTE WRITE and BYTE READ access
cycles.
OPTION
TIMING
30ns
35ns
45ns
60ns
MARKING
-30
-35
-45
-60
will write data into the upper byte (IO9~16).
PIN ASSIGNMENT ( Top View )
Vcc
I/01
I/02
I/03
I/04
Vcc
I/05
I/06
I/07
I/08
NC
NC
WE
RAS
NC
A0
A1
A2
A3
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SOJ
40 Vss
39 I/016
38 I/015
37 I/014
36 I/013
35 Vss
34 I/012
33 I/011
32 I/010
31 I/09
30 NC
29 CASL
28 CASH
27 OE
26 A8
25 A7
24 A6
23 A5
22 A4
21 VSS
PACKAGE
SOJ
TSOP(II)
MARKING
J
S
GENERAL DESCRIPTION
The T224160B is a randomly accessed solid state
memory containing 4,194,304 bits organized in a x16
configuration. The T224160B has both BYTE
WRITE and WORD WRITE access cycles via two
CAS pins. It offers Fast Page mode operation
The T224160B CAS function and timing are
determined by the first CAS to transition low and
by the last to transition back high. Use only one of
the two CAS and leave the other staying high during
WRITE will result in a BYTE WRITE. CASL
transiting low in a WRITE cycle will write data into
the lower byte (IO1~IO8), and CASH transiting low
Taiwan Memory Technology, Inc. reserves the right P. 1
to change products or specifications without notice.
Vcc 1
I/01 2
I/02 3
I/03 4
I/04 5
Vcc 6
I/05 7
I/06 8
I/07 9
I/08 10
NC
NC
WE
RAS
NC
A0
A1
A2
A3
Vcc
11
12
13
14
15
16
17
18
19
20
TSOP(II)
40 Vss
39 I/016
38 I/015
37 I/014
36 I/013
35 Vss
34 I/012
33 I/011
32 I/010
31 I/09
30 NC
29 CASL
28 CASH
27 OE
26 A8
25 A7
24 A6
23 A5
22 A4
21 VSS
Publication Date: MAR. 2001
Revision:B
DataSheet4 U .com







T224160B pdf, 数据表
www.DataSheet4U.com
tm TE
CH
RA S VVIIHL
CA S VVIIHL
A DDR VVIIHL
WE VVIIHL
I/O VVOOHL
OE VVIIHL
READ CYCLE
tR C
tRAS
tRP
tC R P
tR C D
t C SH
t R SH
tCAS
tRRH
tA S R
tR A D
tRAH
RO W
tA R
tA S C
t R AL
tCAH
CO LUMN
tR C S
t RC H
OP EN
tA A
t R AC
t C AC
tCLZ
tO A C
NOTE 1
tOFF 1
V A L ID D A T A
tO FF2
T224160B
ROW
O PE N
EARLY WRITE CYCLE
RAS
V
V
IH
IL
C AS
V
V
IH
IL
A DDR
V
V
IH
IL
tC R P
tA S R
tR A D
tR A H
ROW
WE
V
V
IH
IL
I /O
V
V
IOH
IOL
OE
V
V
IH
IL
tR C
tR A S
t RC D
tC S H
tR S H
tCAS
tA R
tA S C
tRAL
tCAH
CO LUMN
tC W L
tR W L
t WC S
tW C R
tW C H
tW P
tDH R
t DS tDH
V A L ID D A T A
tR P
ROW
DON'T CARE
UNDEFINED
Note: tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last.
Taiwan Memory Technology, Inc. reserves the right P. 8
to change products or specifications without notice.
Publication Date: MAR. 2001
Revision:B
DataSheet4 U .com














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