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PDF ( 数据手册 , 数据表 ) U6239B

零件编号 U6239B
描述 2.9 GHz PLL
制造商 TEMIC Semiconductors
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U6239B 数据手册, 描述, 功能
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U6239B
2.9 GHz PLL for SAT TV Tuner with UNi-Bus
Description
The U6239B is a single-chip frequency synthesizer with
bidirectional I2C bus control and unidirectional 3-wire
bus control, developed for SAT TV-tuner and cable tuner
applications.
This IC contains an integrated preamplifier, a high
frequency prescaler, a reference divider with multiple
programmable divider ratios, a crystal oscillator, a phase/
frequency detector together with a charge pump, a tuning
amplifier and an analog-to-digital converter.
Features
D 2.9 GHz divide-by-16 prescaler integrated
D UNi-BUS:
I2C bus and 3-wire bus
I2C bus software compatible to U6223B
3-wire bus software compatible to LC7215 (Sanyo)
D I2C bus mode:
4 bidirectional ports (open collector)
2 unidirectional ports (open collector)
5 level ADC or unidirectional port (open collector)
Address mode select function (AMS, Pin 3):
3 or 4 addresses selectable via Pin 10
D 3-wire bus mode:
4 unidirectional ports (open collector)
Lock output (open collector)
D Programmable reference divider
D Low power consumption (typ. 5 V / 23 mA)
D Electrostatic protection according to MIL-STD 883
Block Diagram
AS / ENABLE / P3
10
SCL 5
SDA 4
UNI–BUS
Control
5–bit Latch
Vs 12
Power–on
reset POR
GND 15
7–bit Latch
8–bit Latch
7–bit Latch
T1
14–bit Shift Reg.
14
RFi
13
RDS / AMS 3
XTAL 2
Sync 15–bit Latch
T0 5I RD1,2,3
LOCK
div. by 16
Prescaler
AMS SET
RDS
15/14–bit
counter
Oscillator
divide by 256/512/off/1024
divide by 25/50/140/250
divide by 50/100/280/500
Phase
detector
Charge
pump
FP
FR
Figure 1.
ADC
I/O
Ports
11 P0/Lock
9 P4
8 P5
7 P6 / ADC
6 P7
OS
16 VD
1 PD
9611809
TELEFUNKEN Semiconductors
Rev. A3, 28-May-97
1 (15)
DataSheet4 U .com







U6239B pdf, 数据表
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U6239B
I2C Bus Description (continued)
Description
I2C Bus Read Data Format
ÁÁÁASÁÁÁtdadturÁÁÁessbsybÁÁÁteyteÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁMPÁÁÁO1SRBÁÁÁÁÁÁF1LÁÁÁÁÁÁI02ÁÁÁÁÁÁI01ÁÁÁÁÁÁI0ÁÁÁ0 ÁÁÁAAÁÁÁS21ÁÁÁAÁÁÁAS12ÁÁÁÁÁÁLAS10BÁÁÁÁÁÁA–ÁÁÁÁÁÁ
POR :
Power-on reset flag:
POR = 1 on power on
FL : In-lock flag:
FL = 1, when loop is phase locked
I2, I1, I0 : Digital information of I/O-ports P7, P5 and P4 respectively
A2, A1, A0 : Digital data of the 5-level ADC.
see next table
A/D Converter Levels:
I2C Bus Pulse Diagram
Address byte
SDA
A2 A1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ1 0
01
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ0 1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ0 0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ0 0
A0 Input voltage to ADC Pin 9
0 60% Vs to 13.2 V
1 45% to 60% Vs
0 30% to 45% Vs
1 15% to 30% Vs
0 0 V to 15% Vs
/ A / 1.Byte
/ A / 2.Byte
/ A / 3.Byte
/ A / 4.Byte
/A/
9611811
SCL
START 1 2 3 4 5 6 7 8 9 1...
8 9 1...
8 9 1...
8 9 1...
8 9 STOP
Data transfer examples
START – ADR – PDB1 – PDB2 – CB1 – CB2 – STOP
START – ADR – CB1 – CB2 – PDB1 – PDB2 – STOP
START – ADR – PDB1 – PDB2 – CB1 – STOP
START – ADR – PDB1 – PDB2 – STOP
START – ADR – CB1 – CB2 – STOP
START – ADR – CB1 – STOP
Description
START
= Start condition
ADR
= Address byte
PDB1
= Programmable divider byte 1
PDB2
= Programmable divider byte 2
CB1 = Control byte 1
CB2 = Control byte 2
STOP
= Stop condition
8 (15)
DataSheet4 U .com
TELEFUNKEN Semiconductors
Rev. A3, 28-May-97














页数 15 页
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