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零件编号 | DAC8552 | ||
描述 | ULTRA-LOW GLITCH VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER | ||
制造商 | Burr-Brown Corporation | ||
LOGO | |||
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BurrĆBrown Products
from Texas Instruments
DAC8552
DAC8552
SLAS430 – JULY 2006
16-BIT, DUAL CHANNEL, ULTRA-LOW GLITCH VOLTAGE OUTPUT
DIGITAL-TO-ANALOG CONVERTER
FEATURES
DESCRIPTION
• Relative Accuracy: 4LSB
The DAC8552 is a 16-bit, dual channel, voltage
• Glitch Energy: 0.15nV-s
output digital-to-analog converter (DAC) offering low
• MicroPower Operation:
155µA per Channel at 2.7V
• Power-On Reset to Zero-Scale
power operation and a flexible serial host interface.
Each on-chip precision output amplifier allows
rail-to-rail output swing to be achieved over the
supply range of 2.7V to 5.5V. The device supports a
• Power Supply: 2.7V to 5.5V
standard 3-wire serial interface capable of operating
• 16-Bit Monotonic Over Temperature
• Settling Time: 10µs to ±0.003% FSR
• Ultra-Low AC Crosstalk: –100dB Typ
• Low-Power Serial Interface With
with input data clock frequencies up to 30MHz for
VDD = 5V.
The DAC8552 requires an external reference voltage
to set the output range of each DAC channel. Also
incorporated into the device is a power-on reset
Schmitt-Triggered Inputs
circuit which ensures that the DAC outputs power up
• On-Chip Output Buffer Amplifier With
Rail-to-Rail Operation
• Double-Buffered Input Architecture
at zero-scale and remain there until a valid write
takes place. The DAC8552 provides a flexible
power-down feature, accessed over the serial
interface, that reduces the current consumption of
• Simultaneous or Sequential Output Update
the device to 700nA at 5V.
and Powerdown
• Available in a Tiny MSOP-8 Package
The low-power consumption of this device in normal
DataSheet4Uo.pceormation makes it ideally suited for portable
APPLICATIONS
battery-operated equipment and other low-power
applications. The power consumption is 0.5mW per
• Portable Instrumentation
channel at 2.7V, reducing to 1µW in power-down
• Closed-Loop Servo Control
mode.
• Process Control
• Data Acquisition Systems
• Programmable Attenuation
The DAC8552 is available in a MSOP-8 package
with a specified operating temperature range of
–40°C to +105°C.
• PC Peripherals
VDD
VREF
DataShee
Data
Buffer A
DAC
Register A
DAC A
VOUTA
SYNC
SCLK
DIN
Data
Buffer B
DAC
Register B
16
24-Bit,
Serial-to-
Parallel
Shift
Register
8
Channel
Select
Load
Control
Control Logic
GND
DAC B
2
Power-Down
Control Logic
Resistor
Network
VOUTB
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI, QSP are trademarks of Motorola.
DataSheet4UM.cicoromwire is a trademark of National Semiconductor.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
www.DataSheet4U.com
DAC8552
SLAS430 – JULY 2006
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, unless otherwise noted.
www.ti.com
SUPPLY CURRENT vs SUPPLY VOLTAGE
600
550 VREF = VDD, All DAC’s Powered,
Reference Current Included, No Load
500
450
400
350
300
250
200
2.70 3.05 3.40 3.75 4.10 4.45 4.80 5.15 5.50
VDD − Supply Voltage − V
Figure 13.
SUPPLY CURRENT vs TEMPERATURE
600
Reference Current Included
500
VDD = VREF = 5.5V
400
300 VDD = VREF = 3.6V
200
100
0
−40
0 40 80
TA − Free-Air Temperature − °C
Figure 14.
120
et4U.com
SUPPLY CURRENT vs LOGIC INPUT VOLTAGE
SUPPLY CURRENT vs LOGIC INPUT VOLTAGE
800 2400
700 TA = 25°C, SYNC Input (All other inputs = GND)
CH A powered up; All other channels in powerdown
2000
TA = 25°C, SYNC Input (All other inputs = GND)
CH A powered up; All other channels in powerdown
600
500
VDD = VREF = 2.7V
400
1600
DataSheet4U.co1m200
VDD = VREF = 5.5V
300
800
200
400
100
0
0.0 0.5 1.0 1.5 2.0 2.5
0
0.0 1.0 2.0 3.0 4.0 5.0
VLOGIC − Logic Input Voltage − V
Figure 15.
VLOGIC − Logic Input Voltage − V
Figure 16.
−10
−30
−50
−70
−90
−110
−130
0
POWER SPECTRAL DENSITY
VDD = 5V, VREF = 4.096V
fOUT = 1kHz
fCLK = 1MSPS
5000
10000
f − Frequency − Hz
Figure 17.
15000
20000
TOTAL HARMONIC DISTORTION
vs
OUTPUT FREQUENCY
−40
VDD = 5V, VREF = 4.9V
−50
−1dB FSR Digital Input, fS = 1MSPS
Measurement Bandwidth = 20kHz
−60
−70
THD
−80
−90
2nd Harmonic
3rd Harmonic
−100
0
123
Output Tone − kHz
Figure 18.
4
5
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DAC8552
SLAS430 – JULY 2006
www.ti.com
OPERATION EXAMPLES
Example 1: Write to Data Buffer A; Through Buffer B; Load DACA Through DACB Simultaneously
• 1st — Write to DataBuffer A:
Reserved
0
Reserved
0
LDB LDA DC Buffer Select PD1 PD0 DB15 — DB1 DB0
0 0X
0
0 0 D15 — D1
D0
• 2nd — Write to Data Buffer B and Load DAC A and DAC B simultaneously:
Reserved
0
Reserved
0
LDB LDA DC Buffer Select PD1 PD0 DB15 — DB1 DB0
1 1X
1
0 0 D15 — D1
D0
et4U.com
The DACA and DACB analog outputs simultaneously settle to the specified values upon completion of the 2nd
write sequence. (The Load command moves the digital data from the data buffer to the DAC register at which
time the conversion takes place and the analog output is updated. Completion occurs on the 24th falling SCLK
edge after SYNC LOW.)
Example 2: Load New Data to DACA and DACB Sequentially
• 1st — Write to Data Buffer A and Load DAC A: DACA output settles to specified value upon completion:
Reserved
0
Reserved
0
LDB LDA DC Buffer Select PD1 PD0 DB15 — DB1 DB0
0 1X
0
0 0 D15 — D1
D0
• 2nd — Write to Data Buffer B and Load DAC B: DACB output settles to specified value upon completion:
Reserved
0
Reserved
0
LDB LDA DC Buffer Select PD1 PD0 DB15 — DB1 DB0
1 0X
1
0 0 D15 — D1
D0
After completion of the 1st write cycle, the DACA analog output settles to the voltage specified; upon completion
of write cycle 2, the DACB analog output settles.
Example 3: Power-Down DACA to 1kΩ and PDoawtaeSr-hDeoewt4nU.DcoAmCB to 100kΩ Simultaneously
• 1st — Write power-down command to Data Buffer A:
Reserved
0
Reserved
0
LDB LDA DC Buffer Select PD1 PD0 DB15 — DB1 DB0
0 0X
0 01
Don't Care
• 2nd — Write power-down command to Data Buffer B and Load DACA and DACB simultaneously:
Reserved
0
Reserved
0
LDB LDA DC Buffer Select PD1 PD0 DB15 — DB1 DB0
1 1X
1 10
Don't Care
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The DACA and DACB analog outputs simultaneously power-down to each respective specified mode upon
completion of the 2nd write sequence.
Example 4: Power-Down DACA and DACB to High-Impedance Sequentially:
• 1st — Write power-down command to Data Buffer A and Load DAC A: DAC A output = Hi-Z:
Reserved
0
Reserved
0
LDB LDA DC Buffer Select PD1 PD0 DB15 — DB1 DB0
0 1X
0 11
Don't Care
• 2nd — Write power-down command to Data Buffer B and Load DAC B: DAC B output = Hi-Z:
Reserved
0
Reserved
0
LDB LDA DC Buffer Select PD1 PD0 DB15 — DB1 DB0
1 0X
1 11
Don't Care
The DACA and DACB analog outputs sequentially power-down to high-impedance upon completion of the 1st
and 2nd write sequences, respectively.
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页数 | 22 页 | ||
下载 | [ DAC8552.PDF 数据手册 ] |
零件编号 | 描述 | 制造商 |
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