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PDF ( 数据手册 , 数据表 ) T71L6816A

零件编号 T71L6816A
描述 Sixteen-port 10/100 Switch
制造商 Taiwan Memory Technology
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T71L6816A 数据手册, 描述, 功能
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Preliminary T71L6816A
Sixteen-port 10/100 Switch
________________________________________________________
The T71L6816A is a sixteen-port 10/100Mbps dual speed ethernet switch integrated with
a built-in 2K entries of address table and supports a 4Mb external SSRAM. T71L6816A is
also a high performance Fast-Ethernet switch with fully compliance with the IEEE802.3,
802.3u and 802.3x specifications. The T71L6816A can be implemented with external PHY chips
and 4Mb pipe-line SSRAM. By default, it is targeted for applications to the stand -alone
switch for low-cost SOHO and small enterprise market.
Features
l Support sixteen 10/100 Ethernet ports with RMII interface.
l External memory needed for 4Mb pipe-line SSRAM.
l Incorporating with private output buffering scheme to prevent HOL (head of line) blocking.
l Each port support priority-based queues with 4 levels and 802.1p QoS.
l Wire-speed store-and-forward switching with low latency.
l Automatic address learning with filtering of local frames or illegal frames.
l Embedded 2K entries of address look-up table.
l Support full/half duplex operations. DataSheet4U.com
l Support auto-negotiation via MDIO to detect speed and duplex status.
l Serial EEPROM interface for auto-configuration for features.
l Support IEEE802.3x flow control for full-duplex operation.
l Support Back-Pressure flow control for half-duplex operation.
l Support port-trunking mode to aggregate the bandwidth to provide the functions of load-sharing and
link backup.
l Support broadcast storm control scheme.
l Maximum 3 port-based VLAN groups can be defined by user.
l Support port-based port monitoring/snooping defined by user.
l Only one 50Mhz oscillator needed.
l 208-pin BGA, 3.3V with .18 µm CMOS technology.
DataShee
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Change to products or specifications without notice.
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Publication Date:Jun. 2001
Revision:0.A







T71L6816A pdf, 数据表
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Preliminary T71L6816A
3.7 Address
3.7.1 Address Learning
The T71L6816A has a on-chip address table with 2K entries to map the MAC address to
port -ID for the operation of packet forwarding engine. The T71L681 6A use either hash
algorithm or direct mapping to locate every entry and each entry contains the information
about incoming port number, partial MAC address and age timer.
The T71L6816A learns the MAC address of attached network devices by checking the source
MAC address(SA) of all incoming packets and acts as follows: If the SA is an unicast address
and can’t be found in address table, the T71L6816A will allocate an entry for this address
after this packet has been received with no error detected. If the SA was found in address
table, the T71L6806A will update the aging value of the corresponding entry to zero.
et4U.com
The T71L6816A will disable the learning process while the incoming packet is a PAUSE command
defined by IEEE 802.3x.
3.7.2 Address Aging
If the “ AgeEn” option configured in EDEPaRtaOSMhieset4sUet.c,omthe T71L6816A will periodically check
every entry in address table and mark the entry as invalid if its aging timer is over
300 seconds. Once a entry is marked as invalid, this entry no longer be used for address
lookup until it is remarked as valid for new address.
DataShee
3.8 Broadcast Storm Control
In general, the T71L6816A will forward the broadcast packets to other ports. It’s obviously
broadcast packets will use switch resources(bandwidth and available transmit queue) much
more than normal packets. In extreme case of unstable network with something wrong, it
may produce massive broadcast packets from one mal -functional device and results in the
crash of whole network, that is so-called broadcast storm.
If the “BRDCTRL” option configured in EEPROM is set, the T71L6816A provide a scheme to
prevent the broadcast storm by temporarily discarding the broadcast/multicast packets
if the number of those kind of packets exceeds the internal threshold.
DataSheet4U.coTmaiwan Memory Technology, Copy-Right reserved.
Change to products or specifications without notice.
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Publication Date:Jun. 2001
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T71L6816A equivalent, schematic
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Preliminary T71L6816A
Symbol
I/O type Pin Number
Function
TXEN_A ~ TXEN_P
RMII Interfaces (cont.)
O 179, 185, 192, 198, Transmit Enable.
205, 5, 11, 17,
TXEN indicates the MAC is presenting 2-bit data
23, 29, 37, 43,
on TXD[1:0] for transmission.
49, 55, 61, 69
CRSDV_A ~ CRSDV_P I
178, 184, 191, 197, Carrier Sense / Receive Data Valid.
204, 4, 10, 16,
CRSDV indicates the PHY is presenting 2 -bit data
22, 28, 36, 42,
48, 54, 60, 68
on RXD[1:0] for transmission.
MEM_CLK
O 127
SRAM Interfaces
Memory Clock.
AEN_B
O 125
Address Enable.
et4U.com
GWE_B
OE_B
O 124
O 123
Group Write Enable.
DataOSuhtepeut4tUE.cnoamble.
DataShee
SRAM_DATA[63:0]
I/O 72, 73, 74, 75,
SRAM Data Bus.
76, 77, 78, 79,
80, 81, 82, 83,
84, 85, 86, 87,
91, 92, 93, 94,
95, 96, 97, 98,
99, 100, 101, 102,
103, 104, 105, 106,
129, 130, 131, 132,
133, 134, 135, 136,
137, 138, 139, 140,
141, 142, 143, 144,
145, 146, 147, 148,
149, 150, 151, 152,
153, 154, 155, 156,
161, 162, 163, 164
DataSheet4U.coTmaiwan Memory Technology, Copy-Right reserved.
Change to products or specifications without notice.
P. 16
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Publication Date:Jun. 2001
Revision:0.A










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