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PDF ( 数据手册 , 数据表 ) HA-2505

零件编号 HA-2505
描述 12MHz/ High Input Impedance/ Operational Amplifier
制造商 Intersil Corporation
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HA-2505 数据手册, 描述, 功能
Data Sheet
HA-2505
May 1999 File Number 2890.5
12MHz, High Input Impedance,
Operational Amplifier
HA-2505 is an operational amplifier whose design is
optimized to deliver excellent slew rate, bandwidth, and
settling time specifications. The outstanding dynamic
features of this internally compensated device are
complemented with low offset voltage and offset current.
This dielectrically isolated amplifier is ideally suited for
applications such as data acquisition, RF, video, and pulse
conditioning circuits. Slew rates of ±30V/µs and 330ns
(0.1%) settling time make this device an excellent
component in fast, accurate data acquisition and pulse
amplification designs. 12MHz small signal bandwidth and
500kHz power bandwidth make this device well suited to RF
and video applications. With 2mV typical offset voltage plus
offset trim capability and 10nA offset current, HA-2505 is
particularly useful in signal conditioning designs.
The gain and offset voltage figures of the HA-2505 are
optimized by internal component value changes while the
similar design of the HA-2515 is maximized for slew rate.
MIL-STD-883 product and data sheets are available upon
request.
Ordering Information
PART
NUMBER
TEMP RANGE
(oC)
PACKAGE
HA3-2505-5
0 to 75 8 Ld PDIP
PKG. NO.
E8.3
Features
• Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V/µs
• Fast Settling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330ns
• Full Power Bandwidth . . . . . . . . . . . . . . . . . . . . . . 500kHz
• Gain Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . 12MHz
• High Input Impedance . . . . . . . . . . . . . . . . . . . . . . 50M
• Low Offset Current . . . . . . . . . . . . . . . . . . . . . . . . . . 10nA
• Internally Compensated For Unity Gain Stability
Applications
• Data Acquisition Systems
• RF Amplifiers
• Video Amplifiers
• Signal Generators
Pinout
HA-2505 (PDIP)
TOP VIEW
BAL 1
-IN 2
+IN 3
V- 4
-
+
8 COMP
7 V+
6 OUT
5 BAL
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999







HA-2505 pdf, 数据表
HA-2505
Dual-In-Line Plastic Packages (PDIP)
INDEX
AREA
N
12 3
-A-
BASE
PLANE
SEATING
PLANE
D1
B1
B
E1
N/2
-B-
D
-C- A2 A
L
D1
e
A1
eC
0.010 (0.25) M C A B S
E
CL
eA
C
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protru-
sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and eA are measured with the leads constrained to be per-
pendicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads uncon-
strained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
E8.3 (JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
INCHES
MILLIMETERS
SYMBOL MIN MAX MIN MAX NOTES
A
-
0.210
-
5.33 4
A1
0.015
-
0.39
-
4
A2
0.115 0.195 2.93
4.95
-
B
0.014 0.022 0.356 0.558
-
B1
0.045 0.070 1.15
1.77 8, 10
C
0.008 0.014 0.204 0.355
-
D
0.355 0.400 9.01 10.16
5
D1
0.005
-
0.13
-
5
E
0.300 0.325 7.62
8.25
6
E1
0.240 0.280 6.10
7.11
5
e 0.100 BSC
2.54 BSC
-
eA 0.300 BSC
7.62 BSC
6
eB
-
0.430 - 10.92
7
L
0.115 0.150 2.93
3.81
4
N8
89
Rev. 0 12/93
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
8














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