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PDF ( 数据手册 , 数据表 ) VG2617400FJ

零件编号 VG2617400FJ
描述 CMOS DRAM
制造商 Vanguard International Semiconductor
LOGO Vanguard International Semiconductor LOGO 


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VG2617400FJ 数据手册, 描述, 功能
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Description
VG26(V)(S)17400FJ
4,194,304 x 4 - Bit
CMOS Dynamic RAM
The device is CMOS Dynamic RAM organized as 4,194,304 words x 4 bits. It is fabricated
with an advanced submicron CMOS technology and designed to operate from a single 5V only
or 3.3V only power supply. Low voltage operation is more suitable to be used on battery
backup, portable electronic application. A new refresh feature called “ self-refresh “ is supported
and very slow CBR cycles are being performed. It is packaged in JEDEC standard 26/24 - pin
plastic SOJ or TSOP (II).
Features
• Single 5V (±10 %) or 3.3V (+10%,-5%) only power supply
• High speed tRAC access time : 50/60 ns
• Low power dissipation
- Active mode : 5V version 605/550 mW (Max.)
3.3V version 396/360 mW (Max.)
- Standby mode : 5V version 1.375 mW (Max.)
3.3V version 0.54 mW (Max.)
• Fast Page Mode access
• I/O level : TTL compatible (Vcc = 5V)
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LVTTL compatible (Vcc = 3.3V)
• 2048 refresh cycles in 32 ms (Std) or 128ms (S - version)
• 4 refresh mode :
- RAS only refresh
- CAS-before-RAS refresh
- Hidden refresh
- Self - refresh (S - version)
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VG2617400FJ pdf, 数据表
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VG26(V)(S)17400FJ
4,194,304 x 4 - Bit
CMOS Dynamic RAM
DC Characteristics ; 3.3 - Volt Verion
(Ta = 0 to 70°C, VCC = + 3.3V(+10%,-5%), Vss = 0V)
Parameter
Symbol
Test Conditions
VG26 (V) (S) 17400E
-5 -6 Unit Notes
Min Max Min Max
Operating
current
RAS cycling
ICC1 CAS cycling
tRC = min.
- 145 - 135 mA 1, 2
Low
power
S - version
LVTTL interface
RAS, CAS = VIH
Dout = high - Z
- 0.5
- 0.5
mA
Standby Standard
Current power
version
CMOS interface
RAS, CAS VCC - 0.2V
Dout = high - Z
ICC2 LVTTL interface
RAS, CAS = VIH
Dout = high - Z
- 0.15
- 0.15
mA
-2-2
mA
CMOS interface
RAS, CAS VCC - 0.2V
Dout = high - Z
- 0.5
- 0.5
mA
RAS - only
refresh current
ICC3
RAS cycling, CAS = VIH
tRC = min.
- 145
- 135
1, 2
mA
et4U.com
Fast page mode
current
CAS - before - RAS
refresh current
ICC4
tPC = min.
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ICC5 tRC = min.
RAS, CAS cycling
- 100
- 145
- 90
mA
- 135
mA
1,3
1, 2
Self - refresh currant
(S - Version)
ICC8
tRASS 100µS
- 250 - 250 µA
CAS - before - RAS
long refresh
current (S - Version)
ICC9 Standby : VCC - 0.2V RAS
CAS before RAS refresh :
2048 cycles/128ms
RAS, RAS : 0V VIL 0.2V
VCC - 0.2V VIH VIH (Max)
Dout = high - Z, tRAS 300ns
- 300 - 300 µA
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VG2617400FJ equivalent, schematic
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• Delayed Write Cycle
RAS
CAS
tT
tRC
t RAS
tRCD
tCSH
tRSH
tCAS
VG26(V)(S)17400FJ
4,194,304 x 4 - Bit
CMOS Dynamic RAM
tRP
tCRP
tCPN
ADDRESS
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WE
OE
DQ1 ~ DQ4
tASR
tRAH
Row
tASC
tCAH
Column
t RCS
t CWL
t RWL
tWP
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t OED
t DS
tOEH
OPEN
tDS
tDH
DIN
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