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PDF ( 数据手册 , 数据表 ) VG26V17405F

零件编号 VG26V17405F
描述 CMOS DRAM
制造商 Vanguard Microelectronics Limited
LOGO Vanguard Microelectronics Limited LOGO 


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VG26V17405F 数据手册, 描述, 功能
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VIS
Description
VG26(V)(S)17405F
4,194,304 x 4 - Bit
CMOS Dynamic RAM
The device CMOS Dynamic RAM organized as 4,194,304 words x 4 bits with extended data out access
mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single
5V only or 3.3V oniy power supply. Low voltage operation is more suitable to be used on battery backup,
portable electronic application. Self-Refresh is supported and CBR cycles are being performed. lt is pack-
aged in JEDEC standard 26/24-pin plastic SOJ or TSOPII.
Features
Single 5V( ±10 %) or 3.3V(3.15V~3.6V) only power supply
High speed tRAC access time: 50/60ns
Extended - data - out(EDO) page mode access
I/O level: TTL compatible (Vcc = 5V)
LVTTL compatible (Vcc = 3.3V)
4 refresh modes:
- RAS only refresh
- CAS - before - RAS refresh
- Hidden refresh
- Self-refresh
Refresh interval:
DataSheet4U.com
- RAS only refresh, CAS - before - RAS refresh and hidden refresh: 2048 cycles in 32ms
- Self-refresh: 2048 cycles
JEDEC standard pinout: 26/24-pin plastic SOJ and TSOPII.
DataShee
DataSheet4U.com
Document:1G5-0187
DataSheet4 U .com
Rev.2
Page 1







VG26V17405F pdf, 数据表
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VIS
VG26(V)(S)17405F
4,194,304 x 4 - Bit
CMOS Dynamic RAM
DC Characteristics ; 3.3 - Volt Version
(Ta = 0 to 70°C, VCC = + 3.3V(3.15V~3.6V), VSS = 0V)
Parameter
Symbol
Test Conditions
Operating current
Standby Current
RAS- only refresh current
EDO page mode current
ICC1
ICC2
ICC3
ICC4
RAS cycling
CAS cycling
tRC = min
LVTTL interface
RAS, CAS = VIH
Dout = High-Z
CMOS interface
RAS, CAS ³ VCC -0.2V
Dout = High-Z
RAS cycling, CAS = VIH
tRC = min
tPC = min
VG26(V)(S)17405 Unit Notes
-5 -6
Min Max Min Max
- 120
- 110 mA 1, 2
- 2 - 2 mA
- 0.5
- 0.5 mA
- 120
- 90
- 110 mA 1, 2
- 80 mA 1, 3
et4U.comCcuArSre-nbtefore- RAS refresh
Self- refresh current
ICC5 tRC = min DataSheet4U.com - 120
RAS, CAS cycling
ICC8
tRAS ³ 100ms
550
tRAS ³ 100ms (low power
version)
- 350
- 110 mA 1, 2
550 mA
- 350 mA
4
5
Notes:
1. ICC is specified as an average current. It depends on output loading condition and cycle rate when the
device is selected. ICC max is specified at the output open condition.
2. Address can be changed once or less while RAS = VIL.
3. For ICC4, address can be changed once or less within one EDO page mode cycle time.
4. Normal version: VG26VS17405FT, VG26VS17405FJ
5. Low power version: VG26VS17405FTL, VG26VS17405FJL
DataShee
DataSheet4U.com
Document:1G5-0187
DataSheet4 U .com
Rev.2
Page 8







VG26V17405F equivalent, schematic
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VIS
Early Write Cycle
RAS
CAS
ADDRESS
tRC
t RAS
tCSH
tRCD
tT
tRSH
tCAS
tASR
tRAD
tRAH
Row
tRAL
tASC
tCAH
tRAL
Column
VG26(V)(S)17405F
4,194,304 x 4 - Bit
CMOS Dynamic RAM
tRP
tCRP
tCPN
et4U.com
WE
DQ1~DQ4
tWCS
t WCH
DataSheet4U.com
tDS tDH
DIN
DataShee
DataSheet4U.com
Document:1G5-0187
DataSheet4 U .com
Rev.2
Page 16










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