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PDF ( 数据手册 , 数据表 ) DL140

零件编号 DL140
描述 High Performance ECL Data
制造商 On Semiconductor
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DL140 数据手册, 描述, 功能
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DL140/D
Rev. 6, Jan-2001
High Performance ECL Data
ECLinPSand ECLinPS Lite
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DL140 pdf, 数据表
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Numeric Data Sheet Listing (continued)
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Chapter 3: Low Voltage ECLinPS Data Sheets (continued)
Device
Function
Page
MC100LVEL12 . . . . . . . . . . . . . . . 3.3V ECL Low Impedance Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
MC100LVEL13 . . . . . . . . . . . . . . . 3.3V ECL Dual 1:3 Fanout Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
MC100LVEL14 . . . . . . . . . . . . . . . 3.3V ECL 1:5 Clock Distribution Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
MC100LVEL16 . . . . . . . . . . . . . . . 3.3V ECL Differential Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530
MC100LVEL17 . . . . . . . . . . . . . . . 3.3V ECL Quad Differential Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
MC100LVELT22 . . . . . . . . . . . . . . 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator . . . . . . . . . . . . . . . . . . . . . 538
MC100LVELT23 . . . . . . . . . . . . . . 3.3V Dual Differential LVPECL to LVTTL Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
MC100LVEL29 . . . . . . . . . . . . . . . 3.3V ECL Dual Diff Data and Clock D FlipFlop With Set and Reset . . . . . . . . . . . . . . . 546
MC100LVEL30 . . . . . . . . . . . . . . . 3.3V ECL Triple D FlipFlop with Set and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550
MC100LVEL31 . . . . . . . . . . . . . . . 3.3V ECL D FlipFlop with Set and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
MC100LVEL32 . . . . . . . . . . . . . . . 3.3V ECL 2 Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
MC100LVEL33 . . . . . . . . . . . . . . . 3.3V ECL 4 Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563
MC100LVEL37 . . . . . . . . . . . . . . . 3.3V ECL 1:4 1/ 2 Clock Fanout Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
MC100LVEL38 . . . . . . . . . . . . . . . 3.3V ECL 2, 4/6 Clock Generation Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
MC100LVEL39 . . . . . . . . . . . . . . . 3.3V ECL 2/4, 4/6 Clock Generation Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578
MC100LVEL40 . . . . . . . . . . . . . . . 3.3V/5V ECL Differential PhaseFrequency Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
MC100LVEL51 . . . . . . . . . . . . . . . 3.3V ECL Differential Clock D FlipFlop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588
MC100LVEL56 . . . . . . . . . . . . . . . 3.3V ECL Dual Differential 2:1 Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
MC100LVEL58 . . . . . . . . . . . . . . . 3.3V ECL 2:1 Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
MC100LVEL59 . . . . . . . . . . . . . . . 3.3V ECL Triple 2:1 Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602
MC100LVEL90 . . . . . . . . . . . . . . . 3.3V/5V Triple ECL Input to LVPECL Output Translator . . . . . . . . . . . . . . . . . . . . . . . . 606
MC100LVEL91 . . . . . . . . . . . . . . . 3.3V/5V Triple LVPDEaCtaLS/PhEeCeLt4InUp.uctotmo 3.3V ECL Output Translator . . . . . . . . . . . . . . 610
MC100LVEL92 . . . . . . . . . . . . . . . 5V Triple PECL Input to LVPECL Output Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
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DL140 equivalent, schematic
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MC10E016, MC100E016
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FUNCTION TABLE
CE PE TCLD MR CLK
XL X L Z
LH L L Z
LH H L Z
HH X L Z
X X X L ZZ
XX X H X
Z= clock pulse (low to high);
ZZ= clock pulse (high to low)
FUNCTION
Load Parallel (Pn to Qn)
Continuous Count
Count; Load Parallel on TC = LOW
Hold
Masters Respond, Slaves Hold
Reset (Qn : = LOW, TC : = HIGH)
PIN DESCRIPTION
PIN FUNCTION
P0 P7
Q0 Q7
CE
ECL Parallel Data (Preset) Inputs
ECL Data Outputs
ECL Count Enable Control Input
PE ECL Parallel Load Enable Control Input
MR ECL Master Reset
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
PE CE P7 P6 P5 VCCO TC
25 24 23 22 21 20 1
MR 26
9 18 Q7
CLK 27
17 Q6
TCLD 28
VEE 1
28-Lead PLCC
(Top View)
16 VCC
15 Q5
NC 2
14 VCCO
P0 3
13 Q4
P1 4
12 Q3
5 6 7 8 9 10 11
P2 P3 P4 VCCO Q0 Q1 Q2
* All VCC and VCCO pins are tied together on the die.
Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
CLK ECL Clock
TC ECL Terminal Count Output
TCLD
ECL TC-Load Control Input
NC No Connect
VCC, VCCO
VEE
Positive Supply
Negative Supply
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8-BIT BINARY COUNTER LOGIC DIAGRAM
Q0 Q1
Q7
PE
TCLD
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CE
Q0M
MASTER Q0M SLAVE Q0 CE
BIT 0
BIT 1
CQE1QQ02
Q4
Q6
Q3
Q5
BIT 7
PO P1 P7
MR
CLK
BITS 2-6
5
TC
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Note that this diagram is provided for understanding of logic operation only.
It should not be used for propagation delays as many gate functions are achieved internally without incurring a full gate delay.
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