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PDF ( 数据手册 , 数据表 ) KS0708

零件编号 KS0708
描述 64COM/128SEG DRIVE FOR DOT MATRIX LCD
制造商 Samsung semiconductor
LOGO Samsung semiconductor LOGO 


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KS0708 数据手册, 描述, 功能
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KS0708
PRELIMINARY SPECIFICATION
64COM/128SEG DRIVE FOR DOT MATRIX LCD
INTRODUCTION
KS0708 is a single-chip LCD driver LSI for liquid crystal dot-matrix graphic display systems. It incorporates
192 driver circuit for 64 commom and 128 segment and 64x128-bit bit-map RAM. It is capable of interfac-
ing with the microprocessor, accepting 8-bit parallel display data directly from it, and storing data in an
onechip Display Data RAM. And it generates internal signals for using LCD driving independent of micro-
processor clock.
FEATURES
¡Ü 64-Channel COMMON & 128-Channel SEGMENT Driver for DOT matrix LCD
¡Ü On-chip display data RAM : 64 X 128 = 8192bits
¡Ü Display data is stored in display data RAM from MPU
- RAM bit data : ON(1), OFF(0)
¡Ü Internal timing generator circuit for dynamic display
¡Ü 8-bit parallel bi-directional data bus
¡Ü Applicable LCD duty : 1/64
¡Ü Power supply voltages : Power supply voltage range : 4.5 ~ 5.5 V(VDD)
LCD Driving voltage range : 8.0 ~ 17.0 V(VLCD = VDD - VEE)
¡Ü Wide operating temperature range : Ta = -30 ¡É ~ 85¡É
¡Ü High Voltage CMOS process
¡Ü Package : available bumped chip
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M/M-96-D001
97-09-19
1







KS0708 pdf, 数据表
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KS0708
PRELIMINARY SPECIFICATION
64COM/128SEG DRIVE FOR DOT MATRIX LCD
FUNCTIONAL DESCRIPTION
Chip Select input
The KS0708 has two chip select pin, CS1B and CS2B. It can interface with a mircoprocessor when these
pins(CS1B or CS2B)is Low. When both of these pins are set to High, DB0 to DB7 are high impedance
and RS, RW, and E inputs are disabled. CS1B pin controls the display status of S1 to S64, and CS2B
does that of S65 to S128. When CS1B and CS2B are Low at the same time, it is impossible to execute
read operation. Therefore one of CS1B or CS2B should be set to Low((CS1B = ¡¨H¡¨& CS2B = ¡¨L¡¨)or
(CS1B = ¡¨L¡¨ & CS2B = ¡¨H¡¨)) in read operation. The RESETB signal is entered independet of the sta-
tus of Chip Select.
et4U.com
CS1B
H
L
H
L
CS2B
H
H
L
L
Read Operation
CS1 CS2
XX
¡Û X
X ¡Û
--
Write Operation
CS1 CS2
XX
¡Û X
X ¡Û
¡Û ¡Û
( - : Not RecommendDeadt,a¡SÛh:eOetp4eUra.ctoiomn, X : No Operation)
Table 1. Relationship between Chip Select pins and Read/Write Operation
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Microprocessor Interface
KS0708 transfers 8-bit parallel in either direction between the controlling microprocessor and the KS0708
through the 8-bit I/O buffer(DB0 TO DB7).
RS, RW and E identify the type of parallel data transfer to be made as shown in table 2.
RS RW
HH
HL
LH
LL
Description
Display data read
Display data write
Status read
Writes to internal register (Instruction)
Table 2. Microprocessor Interface
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M/M-96-D001
97-09-19
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KS0708 equivalent, schematic
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KS0708
PRELIMINARY SPECIFICATION
64COM/128SEG DRIVE FOR DOT MATRIX LCD
INSTRUCTION DESCRIPTION
Instruction Table
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Instruction
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Function
Read display data
1
Write display data
1
Status Read
0
Set Column Address
0
Set Display Start Line 0
Set Page Address
0
Display ON/OFF
0
Reads data (DB[0:7])
1
Read data
from display data RAM to
the data bus.
Writes data(DB[0:7]) into
display data RAM. After
0
Write data
writing instruction, column
address is incremented by
1 automatically.
1 BUSY 0 ON/ RE- 0 0 0
OFF SET
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00 1
Column address (0 ~ 63)
Reads status
BUSY
-0 : Ready
-1 : In operation
0 ON/OFF
-0 : Display ON
-1 : Display OFF
RESET
-0 : Normal
-1 : Reset
Sets the Column address
at the Column address
counter
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01 1
Display Start Line (0 ~ 63)
Indicates the display data
RAM displayed at the top
of the screen.
0 1 0111
Page (0 ~ 7)
Sets the Page address at
the Page address register.
Controls the display on or
off. Internal status and
0 0 0 1 1 1 1 1 0/1 display RAM data is not
affected.
L:OFF, H:ON
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M/M-96-D001
97-09-19
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