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PDF ( 数据手册 , 数据表 ) STA323W

零件编号 STA323W
描述 2.1 channel high-efficiency digital audio system
制造商 ST Microelectronics
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STA323W 数据手册, 描述, 功能
STA323W
2.1 channel high-efficiency digital audio system
PowerSO-36
(slug down)
Features
Wide supply voltage range (10 V - 36 V)
Three power output configurations
– 2 x 10 W + 1 x 20 W
– 2 x 20 W
– 1 x 40 W
Thermal protection
Under-voltage protection
Short-circuit protection
PowerSO-36 slug down package
2.1 channels of 24-bit DDX®
100-dB SNR and dynamic range
32 kHz to 192 kHz input sample rates
Digital gain/attenuation +48 dB to -80 dB in
0.5-dB steps
Four 28-bit user programmable biquads (EQ)
per channel
I²C control
2-channel I²S input data interface
Individual channel and master gain/attenuation
Individual channel and master soft and hard
mute
Datasheet - production data
Individual channel volume and EQ bypass
DDX® POP free operation
Bass/treble tone control
Dual independent programmable
limiters/compressors
AutoModes™ settings for:
– 32 preset EQ curves
– 15 preset crossover settings
– Auto volume controlled loudness
– 3 preset volume curves
– 2 preset anti-clipping modes
– Preset night-time listening mode
– Preset TV AGC
Input and output channel mapping
AM noise-reduction and PWM frequency
shifting modes
Soft volume update and muting
Auto zero detect and invalid input detect
muting selectable DDX® ternary or binary
PWM output plus variable PWM speeds
Selectable de-emphasis
Post-EQ user programmable mix with default
2.1 bass-management settings
Variable max power correction for lower
full-power THD
Four output routing configurations
Selectable clock input ratio
96 kHz internal processing sample rate, 24 to
28-bit precision
Video application supports 576 * fs input mode
Table 1. Device summary
Order code
Package
STA323W13TR
PowerSO-36 in tape & reel
February 2014
This is information on a product in full production.
DocID11535 Rev 7
1/78
www.st.com







STA323W pdf, 数据表
List of figures
List of figures
STA323W
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
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Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Channel signal flow diagram through the digital core . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Channel signal flow diagram through the EQ block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Output power stage configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Schematic for 2 (half-bridge) channels + 1 (full-bridge) channel . . . . . . . . . . . . . . . . . . . . 12
Power schematic for 2 (full-bridge) channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power schematic for 1 mono parallel channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Package pins (viewed from top of device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Test circuit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Test circuit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Recommended power up and power down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Stereo mode - output power vs. supply voltage, THD+N = 10% . . . . . . . . . . . . . . . . . . . . 21
Output power vs. supply for stereo bridge, THD+N=1% . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Half-bridge binary mode output power vs. supply, THD+N=10% . . . . . . . . . . . . . . . . . . . 22
Half-bridge binary mode output power vs. supply voltage, THD+N=1% . . . . . . . . . . . . . . 22
Typical efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Typical frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
FFT -60 dB, 1 kHz output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
FFT inter-modulation distortion 19 kHz and 20 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Frequency response, 1 W, BTL, 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Channel separation, 1 W, BTL stereo mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
THD vs. output power, BTL, 1 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
THD vs. frequency, 1 W output, stereo mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
THD vs. frequency, BTL, 16 W output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
FFT 0 dBFS 1 kHz, 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
FFT 0 dBFS 1 kHz, 6  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
FFT 0 dBFS 1 kHz, 4  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
FFT -60 dBFS 1 kHz, 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
FFT -60 dBFS 1 kHz, 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
FFT -60 dBFS 1 kHz, 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PSRR BTL, 500 mV ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Frequency response, 1 W, binary half-bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Channel separation, 1 W, half bridge binary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
THD+N vs. output power, single ended, 1 kHz, half-bridge binary . . . . . . . . . . . . . . . . . . . 29
THD vs. frequency, single ended, 1 W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
THD vs. frequency, single ended, 8 W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
FFT 0 dB, 1 kHz, single ended, 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
FFT 0 dB, 1 kHz, single ended, 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
FFT 0 dB, 1 kHz, single ended, 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
FFT -60 dB, single ended, 1 kHz, 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
FFT -60 dB, single ended, 1 kHz, 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
FFT -60 dB, single ended, 1 kHz, 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PSRR single ended, 500 mV ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
I²C write procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
I²C read procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
General serial input and output formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Serial input and data timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Basic limiter and volume flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
8/78 DocID11535 Rev 7







STA323W equivalent, schematic
Pin out
STA323W
CLK (pin 27)
This is the master clock input used by the digital core. The master clock must be an integer
multiple of the LR clock frequency. Typically, the master clock frequency is 12.288 MHz
(256 * fs) for a 48kHz sample rate; it is the default setting at power-up. Care must be taken
to provide the device with the nominal system clock frequency; over-clocking the device
may result in anomalous operation, such as inability to communicate.
PLL_FILTER (pin 26)
This is the connection for the external filter components for the PLL loop compensation.
Refer to the schematic diagram Figure 7: Power schematic for 1 mono parallel channel on
page 13 for the recommended circuit.
BICKI (pin 32)
The serial or bit clock input is for framing each data bit. The bit clock frequency is typically
64 * fs using I²S serial format.
SDI (pin 30)
This is the serial data input where PCM audio information enters the device. Six format
choices are available including I²S, left or right justified, LSB or MSB first, with word widths
of 16, 18, 20 and 24 bits.
LRCKI (pin 31)
The left/right clock input is for data word framing. The clock frequency is at the input sample
rate, fs.
16/78
DocID11535 Rev 7










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