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PDF ( 数据手册 , 数据表 ) TSA5512

零件编号 TSA5512
描述 1.3 GHz Bidirectional I2C-bus controlled synthesizer
制造商 NXP Semiconductors
LOGO NXP Semiconductors LOGO 


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TSA5512 数据手册, 描述, 功能
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INTEGRATED CIRCUITS
DATA SHEET
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TSA5512
1.3 GHz Bidirectional I2C-bus
controlled synthesizer
Product specification
File under Integrated Circuits, IC02
October 1992
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TSA5512 pdf, 数据表
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Philips Semiconductors
1.3 GHz Bidirectional I2C-bus controlled synthesizer
Product specification
TSA5512
READ mode: R/W = 1 (see Table 2)
Data can be read out of the TSA5512 by setting the R/W bit to 1. After the slave address has been recognized, the
TSA5512 generates an acknowledge pulse and the first data byte (status word) is transferred on the SDA line (MSB first).
Data is valid on the SDA line during a high position of the SCL clock signal. A second data byte can be read out of the
TSA5512 if the processor generates an acknowledge on the SDA line. End of transmission will occur if no acknowledge
from the processor occurs. The TSA5512 will then release the data line to allow the processor to generate a STOP
condition. When ports P3 to P7 are used as inputs, they must be programmed in their high-impedance state. The POR
flag (power-on reset) is set to 1 when VCC goes below 3 V and at power-on. It is reset when an end of data is detected
by the TSA5512 (end of a READ sequence). Control of the loop is made possible with the in-lock flag FL which indicates
(FL = 1) when the loop is phase-locked. The bits I2, I1 and I0 represent the status of the I/O ports P7, P5 and P4
respectively. A logic 0 indicates a LOW level and a logic 1 a HIGH level (TTL levels). A built-in 5-level ADC is available
on I/O port P6. This converter can be used to feed AFC information to the controller from the IF section of the television
as illustrated in the typical application circuit (Fig.8). The relationship between bits A2, A1 and A0 and the input voltage
on port P6 is given in Table 3.
Table 2 Read data format
Address
Status byte
MSB
LSB
1 1 0 0 0 MA1 MA0 1 A
POR FL I2 I1 I0 A2 A1 A0
byte 1
byte 2
Note to Table 2
et4U.com
POR
FL
I2, I1, I0
A2, A1 A0
power-on reset flag. (POR = 1 on power-on)
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in-lock flag (FL = 1 when the loop is phase-locked)
digital information for I/O ports P7, P5 and P4 respectively
digital outputs of the 5-level ADC. Accuracy is 1/2 LSB (see Table 3)
MSB is transmitted first
DataShee
Address selection
The module address contains programmable address bits (MA1 and MA0) which together with the I/O port P3 offers the
possibility of having several synthesizers (up to 3) in one system.
The relationship between MA1 and MA0 and the input voltage I/O port P3 is given in Table 4
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TSA5512 equivalent, schematic
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Philips Semiconductors
1.3 GHz Bidirectional I2C-bus controlled synthesizer
SO16: plastic small outline package; 16 leads; body width 3.9 mm
Product specification
TSA5512
SOT109-1
et4U.com
y
Z
16
D
pin 1 index
1
e
EA
X
c
HE
vM A
9
DataSheet4U.com A2
A1
8
bp
wM
Q
(A3)
A
Lp
L
detail X
θ
DataShee
0 2.5 5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
UNIT max. A1 A2 A3 bp
c D(1) E (1) e
HE
L
Lp
Q
v
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
inches
0.069
0.010
0.004
0.057
0.049
0.01
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.050
0.244
0.228
0.041
0.039
0.016
0.028
0.020
0.01
w y Z (1)
0.25 0.1
0.7
0.3
0.01
0.004
0.028
0.012
θ
8o
0o
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE
VERSION
SOT109-1
IEC
076E07S
REFERENCES
JEDEC
EIAJ
MS-012AC
EUROPEAN
PROJECTION
ISSUE DATE
95-01-23
97-05-22
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