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PDF ( 数据手册 , 数据表 ) D45128163G5

零件编号 D45128163G5
描述 UPD45128163G5
制造商 NEC
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D45128163G5 数据手册, 描述, 功能
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD45128441, 45128841, 45128163
128M-bit Synchronous DRAM
4-bank, LVTTL
Description
The µPD45128441, 45128841, 45128163 are high-speed 134,217,728-bit synchronous dynamic random-access
memories, organized as 8,388,608 × 4 × 4, 4,194,304 × 8 × 4, 2,097,152 × 16 × 4 (word × bit × bank), respectively.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).
These products are packaged in 54-pin TSOP (II).
Features
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
Pulsed interface
Possible to assert random column address in every cycle
Quad internal banks controlled by BA0(A13) and BA1(A12)
Byte control (×16) by LDQM and UDQM
Programmable Wrap sequence (Sequential / Interleave)
Programmable burst length (1, 2, 4, 8 and full page)
Programmable /CAS latency (2 and 3)
Automatic precharge and controlled precharge
CBR (Auto) refresh and self refresh
• ×4, ×8, ×16 organization
Single 3.3 V ± 0.3 V power supply
LVTTL compatible inputs and outputs
4,096 refresh cycles / 64 ms
Burst termination by Burst stop command and Precharge command
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M12650EJBV0DS00 (11th edition)
Date Published April 2000 NS CP (K)
Printed in Japan
The mark shows major revised points.
©
1997







D45128163G5 pdf, 数据表
www.DataSheet4U.com
µPD45128441, 45128841, 45128163
CONTENTS
1. Input / Output Pin Function ............................................................................................................ 10
2. Commands ....................................................................................................................................... 11
3. Simplified State Diagram ................................................................................................................ 14
4. Truth Table ....................................................................................................................................... 15
4.1 Command Truth Table............................................................................................................................. 15
4.2 DQM Truth Table ...................................................................................................................................... 15
4.3 CKE Truth Table....................................................................................................................................... 15
4.4 Operative Command Table .................................................................................................................... 16
4.5 Command Truth Table for CKE ............................................................................................................. 19
5. Initialization ...................................................................................................................................... 20
6. Programming the Mode Register ................................................................................................... 21
7. Mode Register .................................................................................................................................. 22
7.1 Burst Length and Sequence .................................................................................................................. 23
8. Address Bits of Bank-Select and Precharge ................................................................................ 24
9. Precharge ......................................................................................................................................... 25
10. Auto Precharge ................................................................................................................................ 26
10.1 Read with Auto Precharge .................................................................................................................. 26
10.2 Write with Auto Precharge .................................................................................................................. 27
11. Read / Write Command Interval ..................................................................................................... 28
11.1 Read to Read Command Interval ........................................................................................................ 28
11.2 Write to Write Command Interval ....................................................................................................... 28
11.3 Write to Read Command Interval ........................................................................................................ 29
11.4 Read to Write Command Interval ........................................................................................................ 30
12. Burst Termination ........................................................................................................................... 31
12.1 Burst Stop Command .......................................................................................................................... 31
12.2 Precharge Termination ........................................................................................................................ 32
12.2.1 Precharge Termination in READ Cycle .................................................................................... 32
12.2.2 Precharge Termination in WRITE Cycle .................................................................................. 33
8 Data Sheet M12650EJBV0DS00







D45128163G5 equivalent, schematic
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µPD45128441, 45128841, 45128163
4.4 Operative Command Table Note1
(1/3)
Current state
Idle
Row active
Read
Write
/CS /RAS /CAS /WE Address
H × × ××
L H H ××
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA
L L H L BA, A10
L L L H×
L L L L Op-Code
H × × ××
L H H ××
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA
L L H L BA, A10
L L L H×
L L L L Op-Code
H × × ××
L H H H×
L H H L×
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA
L L H L BA, A10
L L L H×
L L L L Op-Code
H × × ××
L H H H×
L H H L×
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA
L L H L BA, A10
L L L H×
L L L L Op-Code
Command
DESL
NOP or BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP or BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
Action
Nop or power down
Nop or power down
ILLEGAL
ILLEGAL
Row activating
Nop
CBR (auto) refresh or self refresh
Mode register accessing
Nop
Nop
Begin read : Determine AP
Begin write : Determine AP
ILLEGAL
Precharge
ILLEGAL
ILLEGAL
Continue burst to end Row active
Continue burst to end Row active
Burst stop Row active
Terminate burst, new read : Determine AP
Terminate burst, start write : Determine AP
ILLEGAL
Terminate burst, precharging
ILLEGAL
ILLEGAL
Continue burst to end Write recovering
Continue burst to end Write recovering
Burst stop Row active
Terminate burst, start read : Determine AP
Terminate burst, new write : Determine AP
ILLEGAL
Terminate burst, precharging
ILLEGAL
ILLEGAL
Notes
2
2
3
3
4
5
5
3
6
7
7, 8
3
7, 8
7
3
9
16 Data Sheet M12650EJBV0DS00










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