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PDF ( 数据手册 , 数据表 ) T8208

零件编号 T8208
描述 ATM Interconnect
制造商 Agere Systems
LOGO Agere Systems LOGO 


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T8208 数据手册, 描述, 功能
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Advance Data Sheet
September 2001
CelXpresTM T8208
ATM Interconnect
1 Product Overview
s Programmable priority for control/data cells trans-
mission onto cell bus
1.1 Features
s Microprocessor access to all headers of control
cell
s OC-12 data throughput on UTOPIA (16-bit)
(independently on RX and TX UTOPIA)
s Shared UTOPIA mode
s Ability to clear counters on read
s Simplified looping to any system device with a sin-
gle register programming
s UTOPIA Level 1 and 2 (8-bit/16-bit) cell-level
handshake interface (ATM or PHY layers)
s Multi-PHY (MPHY) operation
s UTOPIA clock sourcing with additional settings
s Programmable operations and maintenance and
resource management (OAM/RM) cell routing
s Programmable ATM layer supports up to 64 PHY
ports
s Support of multicast and broadcast cells per PHY
s Egress SDRAM buffer support to extend UTOPIA
s Optional monitoring of misrouted cells
output priority queues for 32K to 512K cells:
s Counters for dropped cells per queue
— 128 queues configurable up to four queues per
PHY with programmable sizes
s Digital loopback before cell bus
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— Programmable number of UTOPIA output
s Microprocessor interface, supporting both Motor-
queues with four levels of priority DataSheet4U.com ola® and Intel® modes (multiplexed and nonmulti-
s Support of ATM traffic management via partial
plexed)
packet discard (PPD), forward explicit congestion s Control cell transmission and reception through
notification (FECN), and the cell loss priority (CLP)
microprocessor port
bit s Single 3.3 V power supply
s Programmable slew rate GTL+ I/O:
— Programmable as bus arbiter
— 1.7 Gbits/s cell bus operation
s 3.3 V TTL I/O (5 V tolerant)
s 272-pin plastic ball grid array (PBGA) package
s Flexible per port cell counters
s Cell header insertion with virtual path identifier
(VPI) and virtual channel identifier (VCI) translation
via external SRAM (up to 64K entries)
s Support of network node interface (NNI) and user
network interface (UNI) header types with optional
generic flow-control (GFC) insertion
s Industrial temperature range (–40 °C to +85 °C)
s Hot insertion capability
s Eight GPIO pins
s JTAG support
s Compatible with Transwitch CellBus®
s Optional sourcing of cell bus clocks from device
s LUT bypass option
1.2 Applications
s TX UTOPIA cell buffer increased to 256 cells for
better queue management with SDRAM queue
bypass option
s Ability for cell bus arbiter to mask devices on the
cell bus
s Ability to modify cell bus priority based on RX PHY
FIFO thresholds
s Asymmetric digital subscriber line (ADSL) digital
subscriber line access multiplexers (DSLAMs)
s Access gateways
s Access multiplexers/concentrators
s Multiservice platforms
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T8208 pdf, 数据表
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CelXpres T8208
ATM Interconnect
Advance Data Sheet
September 2001
List of Tables (continued)
Tables
Pages
Table 156. SDRAM Interrupt Enable (SIE) (0404h) ................................................................................................179
Table 157. SDRAM Configuration (SCF) (0408h) ...................................................................................................180
Table 158. Refresh (RFRSH) (0410h) .....................................................................................................................181
Table 159. Refresh Lateness (RFRSHL) (0412h) ...................................................................................................181
Table 160. Idle State 1 (IS1) (0420h) ......................................................................................................................181
Table 161. Idle State 2 (IS2) (0422h) ......................................................................................................................181
Table 162. Manual Access State 1 (MAS1) (0424h) ...............................................................................................182
Table 163. Manual Access State 2 (MAS2) (0426h) ...............................................................................................182
Table 164. SDRAM Interrupt Service Request 7 (SISR7) (0430h) .........................................................................183
Table 165. SDRAM Interrupt Service Request 6 (SISR6) (0432h) .........................................................................183
Table 166. SDRAM Interrupt Service Request 5 (SISR5) (0434h) .........................................................................183
Table 167. SDRAM Interrupt Service Request 4 (SISR4) (0436h) ......................................................................... 183
Table 168. SDRAM Interrupt Service Request 3 (SISR3) (0438h) .........................................................................184
Table 169. SDRAM Interrupt Service Request 2 (SISR2) (043Ah) .........................................................................184
Table 170. SDRAM Interrupt Service Request 1 (SISR1) (043Ch) .........................................................................184
Table 171. SDRAM Interrupt Service Request 0 (SISR0) (043Eh) .........................................................................184
Table 172. Queue X (QX) (0440h to 053Eh) ...........................................................................................................185
Table 173. Queue X Definition Structure (QXDEF) (2000h to 2FFEh) ....................................................................187
Table 174. Control Cell Receive Extended Memory (CCRXEM) (07FCh to 0832h) ................................................190
Table 175. Control Cell Transmit Extended Memory (CCTXEM) (0900h to 0936h) ................................................190
Table 176. PHY Port 0 and Control Cells Multicast Extended Memory (PP0MEM) (0C00h to 0C1Eh) ...................191
et4U.comTable 177. PHY Port X Multicast Memory (PPXMM) (0C20h to 0FFEh) .................................................................192
Table 178. PPD Memory (PPDM) (1000h to 13FEh) ..............................................................................................193
Table 179. Queue X Dropped Cell Count (QXDCC) (D30a0ta0Shhteoe3t41UFE.cho)m.................................................................194
Table 180. Translation RAM Memory (TRAM) (100000h to 17FFFEh) ....................................................................197
Table 181. SDRAM (SDRAM) (2000000h to 3FFFFFEh) .......................................................................................197
Table 182. Maximum Rating Parameters and Values ..............................................................................................198
Table 183. Recommended Operating Conditions ....................................................................................................198
Table 184. HBM ESD Threshold ..............................................................................................................................198
Table 185. Crystal Specifications ............................................................................................................................199
Table 186. External Clock Requirements .................................................................................................................199
Table 187. dc Electrical Characteristics ..................................................................................................................200
Table 188. Input Clocks ..........................................................................................................................................201
Table 189. Output Clocks ........................................................................................................................................201
Table 190. Nonmultiplexed Intel Mode Write Access Timing ..................................................................................203
Table 191. Nonmultiplexed Intel Mode Read Access Timing ..................................................................................203
Table 192. Motorola Mode Write Access Timing .....................................................................................................205
Table 193. Motorola Mode Read Access Timing .....................................................................................................205
Table 194. Multiplexed Intel Mode Write Access Timing .........................................................................................207
Table 195. Multiplexed Intel Mode Read Access Timing .........................................................................................207
Table 196. TX UTOPIA Timing (70 pF Load on Outputs) .......................................................................................208
Table 197. RX UTOPIA Timing (70 pF Load on Outputs) .......................................................................... ............208
Table 198. External LUT Memory Read Timing (cyc_per_acc = 2) ........................................................................210
Table 199. External LUT Memory Read Timing (cyc_per_acc = 3) ........................................................................210
Table 200. External LUT Memory Write Timing (cyc_per_acc = 2) ........................................................................210
Table 201. External LUT Memory Write Timing (cyc_per_acc = 3) ........................................................................210
Table 202. Cell Bus Timing .....................................................................................................................................211
Table 203. SDRAM Interface Timing .......................................................................................................................212
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T8208 equivalent, schematic
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CelXpres T8208
ATM Interconnect
Advance Data Sheet
September 2001
2 Pinout (continued)
Table 3. Cell Bus Pins
Symbol
ua*[4:0]
cb_d*[31:0]
cb_wc*
cb_rc*
et4U.com cb_fs*
cb_ack*
arb_en*
cb_disable*
cb_iref
cb_vref
cb_vref_vss
cb_gen_wc
cb_gen_rc
Ball
B18, B17, C17, D16,
A18
B5, C6, D7, A5, B6,
C7, A6, B7, A7, C8,
B8, A8, D9, C9, B9,
A9, A11, C11, B11,
A12, B12, C12, D12,
A13, B13, C13, A14,
B14, C14, A15, B15,
D14
A10
B10
C15
B16
A17
C16
A4
D10
C10
A3
B4
Reset
Value
Z
Z
Z
Type
Name/Description
I Unit Address Lines (Active-Low). Address assigned to
device for cell bus identification. TTL compatible input,
5 V tolerant.
I/O Cell Bus Data Lines (Active-Low). GTL+ I/O.
I Cell Bus Write Clock (Active-Low). Uses falling edge
to output data on cell bus. Write and read clocks have
the same frequency but different phase. GTL+ input.
I Cell Bus Read Clock (Active-Low). Uses falling edge
to latch data from cell bus. Write and read clocks have
the same frequency but different phase. GTL+ input.
I/O Cell Bus Frame Sync (Active-Low). GTL+ I/O.
I/O Cell Bus Acknowledge Signal (Active-Low). Driven
DataSlohweeot4nUc.yccolem0 of the following frame when a valid cell is
received from the cell bus. This signal is not driven for
broadcast or multicast cells. GTL+ I/O.
I Cell Bus Arbiter Enable (Active-Low). Cell bus arbiter
enable. Only one device on the cell bus may be config-
ured as arbiter. TTL-compatible input, 5 V tolerant. This
pin has an internal 50 kpull-up resistor.
I Cell Bus Disable (Active-Low). CMOS input that 3-
states all GTL+ outputs when low, but GTL+ buffer inputs
are active. This pin has an internal 50 kpull-up resistor.
I Cell Bus Current Reference. Precision current refer-
ence for GTL+ buffers. A 1 k, 1% resistor must be con-
nected between this pin and GND.
I Cell Bus Voltage Reference. GTL+ buffer threshold
voltage reference (1.0 V typical). This voltage reference
is 2/3 VTT, created using a voltage divider of three 1 k,
1% resistors between VTT and cb_vref_vss.
Cell Bus Voltage Reference Ground.
O Cell Bus Generated Write Clock. TTL Compatible
(+5 V) driver. 10 mA drive. This is the write clock gener-
ated by the T8208 device. Read/write clock delay set by
register 0122h bits[15:13].
O Cell Bus Generated Read Clock. TTL Compatible
(+5 V) driver. 10 mA drive. This is the read clock gener-
ated by the T8208 device. Read/write clock delay set by
register 0122h bits[15:13].
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