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PDF ( 数据手册 , 数据表 ) NM27C64

零件编号 NM27C64
描述 65536-Bit CMOS EPROM
制造商 Fairchild
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NM27C64 数据手册, 描述, 功能
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NMC27C64
65,536-Bit (8192 x 8) CMOS EPROM
January 1999
General Description
The NMC27C64 is a 64K UV erasable, electrically reprogrammable
and one-time programmable (OTP) CMOS EPROM ideally suited
for applications where fast turnaround, pattern experimentation
and low power consumption are important requirements.
The NMC27C64 is designed to operate with a single +5V power
supply with ±10% tolerance. The CMOS design allows the part to
operate over extended and military temperature ranges.
The NMC27C64Q is packaged in a 28-pin dual-in-line package
with a quartz window. The quartz window allows the user to
expose the chip to ultraviolet light to erase the bit pattern. A new
pattern can then be written electrically into the device by following
the programming procedure.
The NMC27C64N is packaged in a 28-pin dual-in-line plastic
molded package without a transparent lid. This part is ideally
suited for high volume production applications where cost is an
important factor and programming only needs to be done once.
This family of EPROMs are fabricated with Fairchild’s proprietary,
time proven CMOS double-poly silicon gate technology which
combines high performance and high density with low power
consumption and excellent reliability.
Features
s High performance CMOS
— 150 ns access time
s JEDEC standard pin configuration
— 28-pin Plastic DIP package
— 28-pin CERDIP package
s Drop-in replacement for 27C64 or 2764
s Manufacturers identification code
Block Diagram
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VCC
GND
VPP
Data Outputs O0 - O7
OE
PGM
CE
Output Enable,
Chip Enable, and
Program Logic
Output
Buffers
A0 - A12
Address
Inputs
Y Decoder
X Decoder
65,536-Bit
Cell Matrix
© 1998 Fairchild Semiconductor Corporation
NMC27C64 Rev. C
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DS008634-1
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NM27C64 pdf, 数据表
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Functional Description
DEVICE OPERATION
The six modes of operation of the NMC27C64 are listed in Table
1. It should be noted that all inputs for the six modes are at TTL
levels. The power supplies required are VCC and VPP. The VPP
power supply must be at 12.75V during the three programming
modes, and must be at 5V in the other three modes. The VCC
power supply must be at 6V during the three programming modes,
and at 5V in the other three modes.
Read Mode
To most efficiently use these two control lines, it is recomended
that CE (pin 20) be decoded and used as the primary device
selecting function, while OE (pin 22) be made a common connec-
tion to all devices in the array and connected to the READ line from
the system control bus. This assures that all deselected memory
devices are in their low power standby modes and that the output
pins are active only when data is desired from a particular memory
device.
Programming
CAUTION: Exceeding 14V on pin 1 (VPP) will damage the
NMC27C64.
The NMC27C64 has two control functions, both of which must be Initially, all bits of the NMC27C64 are in the “1” state. Data is
logically active in order to obtain data at the outputs. Chip Enable introduced by selectively programming “0s” into the desired bit
(CE) is the power control and should be used for device selection. locations. Although only “0s” will be programmed, both “1s” and
Output Enable (OE) is the output control and should be used to “0s” can be presented in the data word. A “0” cannot be changed
gate data to the output pins, independent of device selection. The to a “1” once the bit has been programmed.
programming pin (PGM) should be at VIH except during program-
ming. Assuming that addresses are stable, address access time
(tACC) is equal to the delay from CE to output (tCE). Data is available
at the outputs tOE after the falling edge of OE , assuming that CE
has been low and addresses have been stable for at least tACC
tOE.
The NMC27C64 is in the programming mode when the VPP power
supply is at 12.75V and OE is at VIH. It is required that at least a
0.1 µF capacitor be placed across VPP, VCC to ground to suppress
spurious voltage transients which may damage the device. The
data to be programmed is applied 8 bits in parallel to the data
output pins. The levels required for the address and data inputs
The sense amps are clocked for fast access time. VCC should
therefore be maintained at operating voltage during read and
verify. If VCC temporarily drops below the spec. voltage (but not to
ground) an address transition must be performed after the drop to
are TTL.
For programming, CE should be kept TTL low at all times while VPP
is kept at 12.75V.
insure proper output data.
When the address and data are stable, an active low, TTL program
Standby Mode
pulse is applied to the PGM input. A program pulse must be
applied at each address location to be programmed. The
The NMC27C64 has a standby mode which reduces the active
www.DataSheet4U.compower dissipation by 99%, from 55 mW to 0.55 mW. The
NMC27C64 is programmed with the Fast Programming Algorithm
shown in Figure 1. Each address is programmed with a series of
NMC27C64 is placed in the standby mode by applying a CMOS 100 µs pulses until it verfies good, up to a maximum of 25 pulses.
high signal to the CE input. When in standby mode, the outputs are Most memory cells will program with a single 100 µs pulse. The
in a high impedance state, independent of the OE input.
NMC27C64 must not be programmed with a DC signal applied to
Output OR-Tying
the PGM input.
Because NMC27C64s are usually used in larger memory arrays,
Fairchild has provided a 2-line control function that accommo-
dates this use of multiple memory connections. The 2-line control
function allows for:
1. the lowest possible memory power dissipation, and
2. complete assurance that output bus contention will not
occur.
Programming multiple NMC27C64s in parallel with the same data
can be easily accomplished due to the simplicity of the program-
ming requirements. Like inputs of the paralleled NMC27C64s may
be connected together when they are programmed with the same
data. A low level TTL pulse applied to the PGM input programs the
paralleled NMC27C64s. If an application requires erasing and
reprogramming, the NMC27C64Q UV erasable PROM in a win-
dowed package should be used.
Mode
Pins
Read
Standby
Output Disable
Program
Program Verify
Program Inhibit
CE
(20)
VIL
VIH
Don’t Care
VIL
VIL
VIH
TABLE 1. Mode Selection
OE
(22)
VIL
Don’t Care
VIH
VIH
VIL
Don’t Care
PGM
(27)
VIH
Don’t Care
VIH
VIH
Don’t Care
VPP
(1)
5V
5V
5V
13V
13V
13V
VCC
(28)
5V
5V
5V
6V
6V
6V
Outputs
(11–13, 15–19)
DOUT
Hi-Z
Hi-Z
DIN
DOUT
Hi-Z
NMC27C64 Rev. C
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