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零件编号 | L80227 | ||
描述 | Single chip 100BaseTX/10BaseT PHY | ||
制造商 | LSI Logic | ||
LOGO | |||
1 Page
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TECHNICAL
MANUAL
L80227
www.D1a0tBaASSEh-eT/et4U.com
100BASE-TX
Ethernet PHY
October 2002
®
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2.5.1 100 Mbits/s
2.5.2 10 Mbits/s
2.6 Full-/Half-Duplex Mode
2.6.1 Forcing Full-/Half-Duplex Operation
2.6.2 Full/Half Duplex Indication
2.6.3 Loopback
2.7 10/100 Mbits/s Selection
2.7.1 Forcing 10/100 Mbits/s Operation
2.7.2 Autoselecting 10/100 Mbits/s Operation
2.7.3 10/100 Mbits/s Indication
2.8 Jabber
2.9 Reset
2.10 Receive Polarity Correction
2-32
2-32
2-33
2-34
2-34
2-34
2-35
2-35
2-35
2-36
2-36
2-36
2-37
Chapter 3
Signal Descriptions
3.1 Media Interface Signals
3.2 Controller Interface Signals (MII)
3.3 Management Interface (MI)/LED Signals
www.DataSheet4U.com3.4 LED Signals
3.5 Miscellaneous Signals
3.6 Power Supply
3-2
3-3
3-4
3-6
3-7
3-8
Chapter 4
Registers
4.1 Bit Types
4-1
4.2 MI Serial Port Register Summary
4-3
4.3 Registers
4-5
4.3.1 Control Register (Register 0)
4-5
4.3.2 Status Register (Register 1)
4-7
4.3.3 PHY ID 1 Register (Register 2)
4-9
4.3.4 PHY ID 2 Register (Register 3)
4-10
4.3.5 AutoNegotiation Advertisement Register
(Register 4)
4-11
4.3.6 AutoNegotiation Remote End Capability Register
(Register 5)
4-13
4.3.7 Configuration Register (Register 17)
4-15
viii Contents
Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
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• Descrambler
• 4B5B Decoder/Manchester Decoder
• MII Controller Interface
• Management Interface (MI)
• Collision Detection
Figure 1.1 is a simplified top-level block diagram of the L80227 device.
Figure 1.1 Top Level Block Diagram
OSCIN
Oscillator
4B5B
Encoder
Scrambler
100BASE-TX
Transmitter
L80227
Ethernet
Controller
Manchester
Encoder
10BASE-T
Transmitter
Controller
Interface Collision
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Squelch
TP
Interface
LEDs
Serial
Port
(MI)
LED
Drivers
4B5B
Decoder
Descrambler
Clock & Data
Recovery
Auto-
Negotiation
and Link
Squelch
Clock & Data
Recovery
(Manchester
Decoder)
100BASE-TX
Receiver
10BASE-T
Receiver
Internal output waveshaping circuitry and on-chip filters in the PHY
eliminates the need for external filters normally required in 100BASE-TX
and 10BASE-T applications.
1-2 Introduction
Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
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页数 | 30 页 | ||
下载 | [ L80227.PDF 数据手册 ] |
零件编号 | 描述 | 制造商 |
L80227 | Single chip 100BaseTX/10BaseT PHY | LSI Logic |
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