DataSheet8.cn


PDF ( 数据手册 , 数据表 ) A1020B

零件编号 A1020B
描述 (A1010B / A1020B) FPGAs
制造商 Actel Corporation
LOGO Actel Corporation LOGO 


1 Page

No Preview Available !

A1020B 数据手册, 描述, 功能
www.DataSheet4U.com
ACT1 Series FPGAs
Features
• 5V and 3.3V Families fully compatible with JEDEC
specifications
• Up to 2000 Gate Array Gates (6000 PLD equivalent gates)
• Replaces up to 50 TTL Packages
• Replaces up to twenty 20-Pin PAL® Packages
• Design Library with over 250 Macro Functions
• Gate Array Architecture Allows Completely Automatic
Place and Route
• Up to 547 Programmable Logic Modules
• Up to 273 Flip-Flops
• Data Rates to 75 MHz
• Two In-Circuit Diagnostic Probe Pins Support Speed
Analysis to 25 MHz
• Built-In High Speed Clock Distribution Network
• I/O Drive to 10 mA (5 V), 6 mA (3.3 V)
• Nonvolatile, User Programmable
• Fabricated in 1.0 micron CMOS technology
Description
The ACT™ 1 Series of field programmable gate arrays
(FPGAs) offers a variety of package, speed, and application
combinations. Devices are implemented in silicon gate,
1-micron two-level metal CMOS, and they employ Actel’s
PLICE® antifuse technology. The unique architecture offers
gate array flexibility, high performance, and instant
turnaround through user programming. Device utilization is
typically 95 to 100 percent of available logic modules.
ACT 1 devices also provide system designers with unique
on-chip diagnostic probe capabilities, allowing convenient
testing and debugging. Additional features include an on-chip
mclock driver with a hardwired distribution network. The
.conetwork provides efficient clock distribution with minimum
skew.
t4UThe user-definable I/Os are capable of driving at both TTL
eand CMOS drive levels. Available packages include plastic
eand ceramic J-leaded chip carriers, ceramic and plastic quad
hflatpacks, and ceramic pin grid array.
w.DataSApril 1996
ww © 1996 Actel Corporation
A security fuse may be programmed to disable all further
programming and to protect the design from being copied or
reverse engineered.
Product Family Profile
Device
A1010B A1020B
A10V10B A10V20B
Capacity
Gate Array Equivalent Gates
PLD Equivalent Gates
TTL Equivalent Packages
20-Pin PAL Equivalent Packages
1,200
3,000
30
12
2,000
6,000
50
20
Logic Modules
295 547
Flip-Flops (maximum)
147 273
Routing Resources
Horizontal Tracks/Channel
Vertical Tracks/Column
PLICE Antifuse Elements
22
13
112,000
22
13
186,000
User I/Os (maximum)
57 69
Packages:
44 PLCC 44 PLCC
68 PLCC 68 PLCC
84 PLCC
100 PQFP 100 PQFP
80 VQFP 80 VQFP
84 CPGA 84 CPGA
84 CQFP
Performance
5 V Data Rate (maximum)
3.3 V Data Rate (maximum)
75 MHz
55 MHz
75 MHz
55 MHz
Note: See Product Plan on page 1-286 for package availability.
The Designer and Designer
Advantage™ Systems
The ACT 1 device family is supported by Actel’s Designer and
Designer Advantage Systems, allowing logic design
implementation with minimum effort. The systems offer
Microsoft® Windowsand X Windowsgraphical user
interfaces and integrate with the resident CAE system to
provide a complete gate array design environment: schematic
capture, simulation, fully automatic place and route, timing
verification, and device programming. The systems also
include the ACTmapVHDL optimization and synthesis tool
and the ACTgenMacro Builder, a powerful macro function
generator for counters, adders, and other structural blocks.
1-283







A1020B pdf, 数据表
www.DataSheet4U.com
Equivalent Capacitance
The power dissipated by a CMOS circuit can be expressed by
the Equation 1.
Power (uW) = CEQ * VCC2 * F
(1)
Where:
CEQ is the equivalent capacitance expressed in pF.
VCC is the power supply in volts.
F is the switching frequency in MHz.
Equivalent capacitance is calculated by measuring ICCactive
at a specified frequency and voltage for each circuit
component of interest. Measurements have been made over a
range of frequencies at a fixed value of VCC. Equivalent
capacitance is frequency independent so that the results may
be used over a wide range of operating conditions. Equivalent
capacitance values are shown below.
CEQ Values for Actel FPGAs
Modules (CEQM)
Input Buffers (CEQI)
Output Buffers (CEQO)
Routed Array Clock Buffer
Loads (CEQCR)
A10V10B
A10V20B
3.2
10.9
11.6
A1010B
A1020B
3.7
22.1
31.2
4.1 4.6
To calculate the active power dissipated from the complete
design, the switching frequency of each part of the logic must
be known. Equation 2 shows a piece-wise linear summation
over all components.
Power = VCC2 * [(m * CEQM * fm)modules +
(n * CEQI* fn)inputs + (p * (CEQO+ CL) * fp)outputs +
0.5 * (q1 * CEQCR * fq1)routed_Clk1 +
(r1 * fq1)routed_Clk1]
(2)
Where:
m = Number of logic modules switching at fm
n = Number of input buffers switching at fn
p = Number of output buffers switching at fp
mq1 = Number of clock loads on the first routed array
oclock (All families)
.cr1 = Fixed capacitance due to first routed array
t4Uclock (All families)
www.DataShee1-290
CEQM
CEQI
CEQO
CEQCR
CL
fm
fn
fp
fq1
= Equivalent capacitance of logic modules in pF
= Equivalent capacitance of input buffers in pF
= Equivalent capacitance of output buffers in pF
= Equivalent capacitance of routed array clock in
pF
= Output lead capacitance in pF
= Average logic module switching rate in MHz
= Average input buffer switching rate in MHz
= Average output buffer switching rate in MHz
= Average first routed array clock rate in MHz (All
families)
Fixed Capacitance Values for Actel FPGAs
(pF)
Device Type
r1
routed_Clk1
A1010B
41.4
A1020B
68.6
A10V10B
40
A10V20B
65
Determining Average Switching Frequency
To determine the switching frequency for a design, you must
have a detailed understanding of the data input values to the
circuit. The following guidelines are meant to represent
worst-case scenarios so that they can be generally used to
predict the upper limits of power dissipation. These
guidelines are as follows:
Logic Modules (m)
90% of modules
Inputs switching (n)
#inputs/4
Outputs switching (p)
#outputs/4
First routed array clock loads (q1)
40% of modules
Load capacitance (CL)
35 pF
Average logic module switching rate (fm) F/10
Average input switching rate (fn)
F/5
Average output switching rate (fp)
F/10
Average first routed array clock rate F
(fq1)







A1020B equivalent, schematic
www.DataSheet4U.com
ACT 1 Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
Input Module Propagation Delays
‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3 V Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
tINYH
Pad to Y High
tINYL
Pad to Y Low
Input Module Predicted Routing Delays1
3.1 3.5 4.0 4.7 6.8 ns
3.1 3.5 4.0 4.7 6.8 ns
tIRD1
FO=1 Routing Delay
tIRD2
FO=2 Routing Delay
tIRD3
FO=3 Routing Delay
tIRD4
FO=4 Routing Delay
tIRD8
FO=8 Routing Delay
Global Clock Network
0.9 1.1 1.2 1.4 2.0 ns
1.4 1.7 1.9 2.2 3.2 ns
2.1 2.5 2.8 3.3 4.8 ns
3.1 3.6 4.1 4.8 7.0 ns
6.6 7.7 8.7 10.2 14.8 ns
tCKH
Input Low to High
FO = 16
4.9 5.6 6.4 7.5 6.7
FO = 128
5.6
6.4
7.3
8.6
7.9 ns
tCKL Input High to Low
FO = 16
6.4 7.4 8.4 9.9 8.8
FO = 128
7.0
8.1
9.2 10.8 10.0 ns
tPWH
Minimum Pulse Width FO = 16 6.5
7.5
8.5 10.0 8.9
High
FO = 128 6.8 8.0 9.0 10.5 9.8
ns
tPWL
Minimum Pulse Width FO = 16 6.5
7.5
8.5 10.0 8.9
Low FO = 128 6.8 8.0 9.0 10.5 9.8
ns
tCKSW
Maximum Skew
FO = 16
1.2 1.3 1.5 1.8 1.5
FO = 128
1.8
2.1
2.4
2.8
2.4 ns
tP Minimum Period
FO = 16 13.2 15.4 17.6 20.9 18.2
FO = 128 14.2 16.7 18.9 22.3
20
ns
fMAX
Maximum Frequency
FO = 16
75
65
57
48
55
FO = 128
70
60
53
45
50 MHz
Note:
1. These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to 4 ns.
Routing delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required to
determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior
to shipment.
www1-2.9D8 ataSheet4U.com










页数 24 页
下载[ A1020B.PDF 数据手册 ]


分享链接

Link :

推荐数据表

零件编号描述制造商
A1020Silicon PNP Epitaxial TransistorETC
ETC
A1020PNP Transistor - 2SA1020Toshiba Semiconductor
Toshiba Semiconductor
A1020B(A1010B / A1020B) FPGAsActel Corporation
Actel Corporation
A1020BFPGAsActel
Actel

零件编号描述制造商
STK15C88256-Kbit (32 K x 8) PowerStore nvSRAMCypress Semiconductor
Cypress Semiconductor
NJM4556DUAL HIGH CURRENT OPERATIONAL AMPLIFIERNew Japan Radio
New Japan Radio
EL1118-G5 PIN LONG CREEPAGE SOP PHOTOTRANSISTOR PHOTOCOUPLEREverlight
Everlight


DataSheet8.cn    |   2020   |  联系我们   |   搜索  |  Simemap