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PDF ( 数据手册 , 数据表 ) DQ8020

零件编号 DQ8020
描述 MCC Manchester Code Converter Manual
制造商 LSI Logic
LOGO LSI Logic LOGO 


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DQ8020 数据手册, 描述, 功能
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80820200
MCCTM Manchester
Code Converter
89305
Features
s Compatible with IEEE 802.3 /Ethernet (10BASE5),
IEEE802.3/Cheapernet (10BASE2) and Ethernet
Rev. 1 Specifications
s Compatible with 8003 ELDC®, 8005 Advanced
EDLC
s Manchester Data Encoding/Decoding and
Receiver Clock Recovery with Phase Locked
Loop (PLL)
s Receiver and Collision Squelch Circuit and Noise
Rejection Filter
s Differential TRANSMIT Cable Driver
s Loopback Capability for Diagnostics and
Isolation
s Fail-Safe Watchdog Timer Circuit to Prevent
Continuous Transmission
s 20 MHz Crystal Oscillator
s Transceiver Interface High Voltage (16 V)
Short Circuit Protection
Note: Check for latest Data Sheet revision
before starting any designs.
SEEQ Data Sheets are now on the Web, at
www.lsilogic.com.
This document is an LSI Logic document. Any
reference to SEEQ Technology should be
considered LSI Logic.
s Low Power CMOS Technology with Single 5V
Supply
s 20 pin DIP & PLCC Packages
Description
The SEEQ 8020 Manchester Code Converter chip pro-
vides the Manchester data encoding and decoding func-
tions of the Ethernet Local Area Network physical layer. It
interfaces to the SEEQ 8003 and 8005 Controllers and any
standard Ethernet transceiver as defined by IEEE 802.3
and Ethernet Revision 1.
Functional Block Diagram
TxEN
TxC
TxD
LPBK/
WDTD
CSN
X1
X2
RxC
RxD
COLL
WATCHDOG
TIMER
ENCODER
XTAL
CLOCK
CARRIER
SENSE
DECODER
10MHz
DETECTOR
TRANSMIT
MUX
RECEIVE
COLLISION
Figure 1. 8020 MCC Manchester Code Converter
Block Diagram.
MCC is a trademark of SEEQ Technology Inc.
wwEwD.LDCaistaarSeghiseteeret4d tUra.dceommark of SEEQ Technology Inc.
Pin Configuration
DUAL-IN LINE
TOP VIEW
Tx+
Tx–
VCC
VSS
MODE 1
Rx+
Rx–
MODE 1
GND
1
2
20 V CC
19 Tx+
LPBK/WDTD 3
18 Tx–
Rx+ 4
17 TxD
Rx–
CSN
5
6
8020
16
15
TxC
TxEN
COLL 7
14 X1
RxC 8
13 X2
RxD 9
12 COLL+
VSS 10
11 COLL–
PLASTIC LEADED CHIP CARRIER
TOP VIEW
COLL+
COLL–
3 2 1 20 19
Rx+ 4
Rx– 5
CSN 6
COLL 7
RxC 8
18 Tx–
17 TxD
16 TxC
15 TxEN
14 X1
9 10 11 12 13
MD400023/D
1







DQ8020 pdf, 数据表
www.DataSheet4U.com
Transmit Timing TA = 0°C to 70° C; VCC = 5 V ± 5%
Symbol
Parameter
t [1]
6
t7
t
8
t [1]
9
t [1]
10
t11
t
12
t [1]
13
t [1]
14
t [1]
15
t [1]
16
t17
t [1]
17A
t [1]
17B
t18
t19
t20
TxC Cycle Time
TxC High Time
TxC Low Time
TxC Rise Time
TxC Fall Time
TxEN Setup Time
TxD Setup Time
Bit Center to Bit Center Time
Bit Center to Bit Boundary Time
Tx+ and Tx – Rise Time
Tx+ and Tx – Fall Time
Transmit Active Time From The Last
Positive Transition
From Last Positive Transition of the
Transmit Pair to Differential Output
Approaches within 100 mV of 0 V
From Last Positive Transition of the
Transmit Pair to Differential Output
Approaches within 40 mV of 0 V
Tx+ and Tx– Output Delay Time
TxD Hold Time
TxEN Hold Time
NOTE:
1. Characterized. Not tested.
Min.
99.99
40
40
40
40
99.5
49.5
200
400
15
15
Max.
100.01
5
5
100.5
50.5
5
5
600
7000
70
8020
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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MD400023/D
8














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