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PDF ( 数据手册 , 数据表 ) P-80C32

零件编号 P-80C32
描述 P80C32
制造商 ETC
LOGO ETC LOGO 


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P-80C32 数据手册, 描述, 功能
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80C32/80C52
CMOS 0 to 44 MHz Single Chip 8–bit Microntroller
Description
TEMIC’s 80C52 and 80C32 are high performance CMOS
versions of the 8052/8032 NMOS single chip 8 bit µC.
The fully static design of the TEMIC 80C52/80C32
allows to reduce system power consumption by bringing
the clock frequency down to any value, even DC, without
loss of data.
The 80C52 retains all the features of the 8052 : 8 K bytes
of ROM ; 256 bytes of RAM ; 32 I/O lines ; three 16 bit
timers ; a 6-source, 2-level interrupt structure ; a full
duplex serial port ; and on-chip oscillator and clock
circuits. In addition, the 80C52 has 2 software-selectable
modes of reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the RAM, the timers, the serial port and the interrupt
system continue to function. In the power down mode the
RAM is saved and all other functions are inoperative.
The 80C32 is identical to the 80C52 except that it has no
on-chip ROM. TEMIC’s 80C52/80C32 are manufactured
using SCMOS process which allows them to run from 0
up to 44 MHz with Vcc = 5 V.
TEMIC’s 80C52 and 80C32 are also available at 16 MHz
with 2.7 V < VCC < 5.5 V.
D 80C32 : Romless version of the 80C52
D 80C32/80C52-L16 : Low power version
Vcc : 2.7 – 5.5 V Freq : 0-16 MHz
D 80C32/80C52-12 : 0 to 12 MHz
D 80C32/80C52-16 : 0 to 16 MHz
D 80C32/80C52-20 : 0 to 20 MHz
D 80C32/80C52-25 : 0 to 25 MHz
D 80C32/80C52-30 : 0 to 30 MHz
D 80C32/80C52-36 : 0 to 36 MHz
D 80C32-40 : 0 to 40 MHz*
D 80C32-42 : 0 to 42 MHz*
D 80C32-44 : 0 to 44 MHz*
* 0 to 70°C temperature range.
For other speed and temperature range availability please consult your
sales office.
Features
D Power control modes
D 256 bytes of RAM
D 8 Kbytes of ROM (80C52)
D 32 programmable I/O lines
D Three 16 bit timer/counters
D 64 K program memory space
D 64 K data memory space
D Fully static design
D 0.8µ CMOS process
D Boolean processor
D 6 interrupt sources
D Programmable serial port
D Temperature range : commercial, industrial, automotive,
military
Optional
D Secret ROM : Encryption
D Secret TAG : Identification number
MATRA MHS
Rev. G (14 Jan. 97)
1







P-80C32 pdf, 数据表
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80C32/80C52
The capture mode is illustrated in Figure 7.
Figure 7. Timer 2 in Capture Mode.
with the 16 bit value in registers RCAP2L and RCAP2H,
which are preset by software. If EXEN2 = 1, then Timer
2 still does the above, but with the added feature that a
1-to-0 transition at external input T2EX will also trigger
the 16 bit reload and set EXF2.
The auto-reload mode is illustrated in Figure 8.
Figure 8. Timer in Auto-Reload Mode.
In the auto-reload mode there are again two options,
which are selected by bit EXEN2 in T2CON.If
EXEN2 = 0, then when Timer 2 rolls over it does not only
set TF2 but also causes the Timer 2 register to be reloaded
(MSB)
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
The baud rate generator mode is selected by : RCLK = 1 and/or TCLK = 1.
C/T2
(LSB)
CP/RL2
Symbol
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
Position
T2CON.7
T2CON.6
T2CON.5
T2CON.4
T2CON.3
T2CON.2
T2CON.1
T2CON.0
Name and Significance
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2
will not be set when either RCLK = 1 OR TCLK = 1.
Timer 2 external flag set when either a capture or reload is caused by a negative
transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will
cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by
software.
Receive clock flag. When set, causes the serial port to use Timer2 overflow pulses for its
receive clock in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the
receive clock.
Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for
its transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for
the transmit clock.
Timer 2 external enable flag. When set, allows capture or reload to occur as a result of a
negative transition on T2EX if Timer 2 is not being used to clock the serial port.
EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
Start/stop control for Timer 2. A logic 1 starts the timer.
Timer or counter select. (Timer 2) 0 = Internal timer (OSC/12)
1 = External event counter (falling edge triggered).
Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if
EXEN 2 = 1. When cleared, auto reloads will occur either with Timer 2 overflows or
negative transition at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this
bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
8 MATRA MHS
Rev. G (14 Jan. 97)







P-80C32 equivalent, schematic
www.DataSheet4U.com
80C32/80C52
External Data Memory Characteristics (values in ns)
SYM-
BOL
PARAMETER
TRLRH RD pulse Width
TWLWH WR pulse Width
TLLAX Address Hold After ALE
TRLDV RD to Valid Data in
TRHDX Data hold after RD
TRHDZ Data float after RD
TLLDV ALE to Valid Data In
TAVDV Address to Valid Data IN
TLLWL ALE to WR or RD
TAVWL Address to WR or RD
TQVWX Data valid to WR transition
TQVWH Data Setup to WR transition
TWHQX Data Hold after WR
TRLAZ RD low to Address Float
TWHLH RD or WR high to ALE high
16 MHz 20 MHz 25 MHz 30 MHz 36 MHz 40 MHz 42 MHz 44 MHz
min max min max min max min max min max min max min max min max
340 270 210 180 120 100
90
80
340 270 210 180 120 100
90
80
85 85 70 55 35 30 25 25
240 210 175 135 110
90
80
70
00000000
90 90 80 70 50 45 40 35
435 370 290 235 170 150 140 130
480 400 320 260 190 180 175 170
150 250 135 170 120 130 90 115 70 100 60 95 55 90 50 85
180 180 140 115
75
65
60
55
35 35 30 20 15 10
8
6
380 325 250 215 170 160 150 140
40 35 30 20 15 10
8
6
00000000
35 90 35 60 25 45 20 40 20 40 15 35 13 33 13 33
External Data Memory Write Cycle
TAVWL
TQVWX
External Data Memory Read Cycle
16 MATRA MHS
Rev. G (14 Jan. 97)










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