DataSheet8.cn


PDF ( 数据手册 , 数据表 ) JS28F320J3A

零件编号 JS28F320J3A
描述 Intel StrataFlash Memory (J3)
制造商 Intel Corporation
LOGO Intel Corporation LOGO 


1 Page

No Preview Available !

JS28F320J3A 数据手册, 描述, 功能
( DataSheet : www.DataSheet4U.com )
Intel StrataFlash® Memory (J3)
256-Mbit (x8/x16)
Product Features
Datasheet
Performance
Architecture
— 110/115/120/150 ns Initial Access Speed — Multi-Level Cell Technology: High
— 125 ns Initial Access Speed (256 Mbit
density only)
— 25 ns Asynchronous Page mode Reads
— 30 ns Asynchronous Page mode Reads
(256Mbit density only)
— 32-Byte Write Buffer
—6.8 µs per byte effective
programming time
Software
Density at Low Cost
— High-Density Symmetrical 128-Kbyte
Blocks
—256 Mbit (256 Blocks) (0.18µm only)
—128 Mbit (128 Blocks)
64 Mbit (64 Blocks)
—32 Mbit (32 Blocks)
Quality and Reliability
— Operating Temperature:
-40 °C to +85 °C
— Program and Erase suspend support
— 100K Minimum Erase Cycles per Block
— Flash Data Integrator (FDI), Common
Flash Interface (CFI) Compatible
Security
— 128-bit Protection Register
—64-bit Unique Device Identifier
—64-bit User Programmable OTP Cells
— Absolute Protection with VPEN = GND
— Individual Block Locking
— Block Erase/Program Lockout during
Power Transitions
— 0.18 µm ETOX™ VII Process (J3C)
— 0.25 µm ETOX™ VI Process (J3A)
Packaging and Voltage
— 56-Lead TSOP Package
— 64-Ball Intel® Easy BGA Package
— Lead-free packages available
— 48-Ball Intel® VF BGA Package (32 and
64 Mbit) (x16 only)
— VCC = 2.7 V to 3.6 V
— VCCQ = 2.7 V to 3.6 V
Capitalizing on Intel’s 0.25 and 0.18 micron, two-bit-per-cell technology, the Intel StrataFlash® Memory (J3)
device provides 2X the bits in 1X the space, with new features for mainstream performance. Offered in 256-
Mbit (32-Mbyte), 128-Mbit (16-Mbyte), 64-Mbit, and 32-Mbit densities, the J3 device brings reliable, two-bit-
per-cell storage technology to the flash market segment. Benefits include more density in less space, high-speed
interface, lowest cost-per-bit NOR device, support for code and data storage, and easy migration to future
devices.
Using the same NOR-based ETOX™ technology as Intel’s one-bit-per-cell products, the J3 device takes
advantage of over one billion units of flash manufacturing experience since 1987. As a result, J3 components
are ideal for code and data applications where high density and low cost are required. Examples include
networking, telecommunications, digital set top boxes, audio recording, and digital imaging.
By applying FlashFile™ memory family pinouts, J3 memory components allow easy design migrations from
existing Word-Wide FlashFile memory (28F160S3 and 28F320S3), and first generation Intel StrataFlash®
memory (28F640J5 and 28F320J5) devices.
J3 memory components deliver a new generation of forward-compatible software support. By using the
Common Flash Interface (CFI) and the Scalable Command Set (SCS), customers can take advantage of density
upgrades and optimized write capabilities of future Intel StrataFlash® memory devices. Manufactured on Intel®
0.18 micron ETOX™ VII (J3C) and 0.25 micron ETOX™ VI (J3A) process technology, the J3 memory device
provides the highest levels of quality and reliability.
Notice: This document contains information on new products in production. The specifications are
subject to change without notice. Verify with your local Intel sales office that you have the latest
datasheet before finalizing a design.
Order Number: 290667-021
March 2005
www.DataSheet4U.com







JS28F320J3A pdf, 数据表
256-Mbit J3 (x8/x16)
2.0
Functional Overview
The Intel StrataFlash® memory family contains high-density memories organized as 32 Mbytes or
16Mwords (256-Mbit, available on the 0.18µm lithography process only), 16 Mbytes or 8 Mwords
(128-Mbit), 8 Mbytes or 4 Mwords (64-Mbit), and 4 Mbytes or 2 Mwords (32-Mbit). These
devices can be accessed as 8- or 16-bit words. The 128-Mbit device is organized as one-hundred-
twenty-eight 128-Kbyte (131,072 bytes) erase blocks. The 64-Mbit device is organized as sixty-
four 128-Kbyte erase blocks while the 32-Mbit device contains thirty-two 128-Kbyte erase blocks.
A 128-bit Protection Register has multiple uses, including unique flash device identification.
The device’s optimized architecture and interface dramatically increases read performance by
supporting page-mode reads. This read mode is ideal for non-clock memory systems.
A Common Flash Interface (CFI) permits software algorithms to be used for entire families of
devices. This allows device-independent, JEDEC ID-independent, and forward- and backward-
compatible software support for the specified flash device families. Flash vendors can standardize
their existing interfaces for long-term compatibility.
Scalable Command Set (SCS) allows a single, simple software driver in all host systems to work
with all SCS-compliant flash memory devices, independent of system-level packaging (e.g.,
memory card, SIMM, or direct-to-board placement). Additionally, SCS provides the highest
system/device data transfer rates and minimizes device and system-level implementation costs.
A Command User Interface (CUI) serves as the interface between the system processor and
internal operation of the device. A valid command sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM) automatically executes the algorithms and
timings necessary for block erase, program, and lock-bit configuration operations.
A block erase operation erases one of the device’s 128-Kbyte blocks typically within one second—
independent of other blocks. Each block can be independently erased 100,000 times. Block erase
suspend mode allows system software to suspend block erase to read or program data from any
other block. Similarly, program suspend allows system software to suspend programming (byte/
word program and write-to-buffer operations) to read data or execute code from any other block
that is not being suspended.
Each device incorporates a Write Buffer of 32 bytes (16 words) to allow optimum programming
performance. By using the Write Buffer, data is programmed in buffer increments. This feature can
improve system program performance more than 20 times over non-Write Buffer writes.
Blocks are selectively and individually lockable in-system.Individual block locking uses block
lock-bits to lock and unlock blocks. Block lock-bits gate block erase and program operations.
Lock-bit configuration operations set and clear lock-bits (Set Block Lock-Bit and Clear Block
Lock-Bits commands).
The Status Register indicates when the WSM’s block erase, program, or lock-bit configuration
operation is finished.
The STS (STATUS) output gives an additional indicator of WSM activity by providing both a
hardware signal of status (versus software polling) and status masking (interrupt masking for
background block erase, for example). Status indication using STS minimizes both CPU overhead
and system power consumption. When configured in level mode (default mode), it acts as a RY/
BY# signal. When low, STS indicates that the WSM is performing a block erase, program, or lock-
bit configuration. STS-high indicates that the WSM is ready for a new command, block erase is
8 Datasheet







JS28F320J3A equivalent, schematic
256-Mbit J3 (x8/x16)
4.4 Signal Descriptions
Table 3 describes active signals used.
Table 3. Signal Descriptions (Sheet 1 of 2)
Symbol
A0
A[MAX:1]
D[7:0]
D[15:8]
CE0,
CE1,
CE2
RP#
OE#
WE#
STS
BYTE#
VPEN
VCC
VCCQ
Type
Name and Function
Input
BYTE-SELECT ADDRESS: Selects between high and low byte when the device is in x8 mode.
This address is latched during a x8 program cycle. Not used in x16 mode (i.e., the A0 input buffer
is turned off when BYTE# is high).
Input
ADDRESS INPUTS: Inputs for addresses during read and program operations. Addresses are
internally latched during a program cycle.
32-Mbit: A[21:0]
64-Mbit: A[22:0]
128-Mbit: A[23:0]
256-Mbit: A[24:0]
LOW-BYTE DATA BUS: Inputs data during buffer writes and programming, and inputs
Input/Output commands during CUI writes. Outputs array, CFI, identifier, or status data in the appropriate read
mode. Data is internally latched during write operations.
HIGH-BYTE DATA BUS: Inputs data during x16 buffer writes and programming operations.
Input/Output Outputs array, CFI, or identifier data in the appropriate read mode; not used for Status Register
reads. Data is internally latched during write operations in x16 mode. D[15-8] float in x8 mode
Input
CHIP ENABLES: Activates the device’s control logic, input buffers, decoders, and sense
amplifiers. When the device is de-selected (see Table 13 on page 33), power reduces to standby
levels.
All timing specifications are the same for these three signals. Device selection occurs with the
first edge of CE0, CE1, or CE2 that enables the device. Device deselection occurs with the first
edge of CE0, CE1, or CE2 that disables the device (see Table 13 on page 33).
Input
RESET/ POWER-DOWN: RP#-low resets internal automation and puts the device in power-
down mode. RP#-high enables normal operation. Exit from reset sets the device to read array
mode. When driven low, RP# inhibits write operations which provides data protection during
power transitions.
Input
OUTPUT ENABLE: Activates the device’s outputs through the data buffers during a read cycle.
OE# is active low.
Input
WRITE ENABLE: Controls writes to the CUI, the Write Buffer, and array blocks. WE# is active
low. Addresses and data are latched on the rising edge of WE#.
Open Drain
Output
STATUS: Indicates the status of the internal state machine. When configured in level mode
(default), it acts as a RY/BY# signal. When configured in one of its pulse modes, it can pulse to
indicate program and/or erase completion. For alternate configurations of the STATUS signal,
see the Configurations command. STS is to be tied to VCCQ with a pull-up resistor.
Input
BYTE ENABLE: BYTE#-low places the device in x8 mode; data is input or output on D[7:0],
while D[15:8] is placed in High-Z. Address A0 selects between the high and low byte. BYTE#-
high places the device in x16 mode, and turns off the A0 input buffer. Address A1 becomes the
lowest-order address bit.
Input
Power
Power
ERASE / PROGRAM / BLOCK LOCK ENABLE: For erasing array blocks, programming data, or
configuring lock-bits.
With VPEN VPENLK, memory contents cannot be altered.
CORE POWER SUPPLY: Core (logic) source voltage. Writes to the flash array are inhibited
when VCC VLKO. Device operation at invalid Vcc voltages should not be attempted.
I/O POWER SUPPLY: I/O Output-driver source voltage. This ball can be tied to VCC.
16 Datasheet










页数 30 页
下载[ JS28F320J3A.PDF 数据手册 ]


分享链接

Link :

推荐数据表

零件编号描述制造商
JS28F320J3AIntel StrataFlash Memory (J3)Intel Corporation
Intel Corporation
JS28F320J3D-75Numonyx Embedded Flash MemoryIntel Corporation
Intel Corporation

零件编号描述制造商
STK15C88256-Kbit (32 K x 8) PowerStore nvSRAMCypress Semiconductor
Cypress Semiconductor
NJM4556DUAL HIGH CURRENT OPERATIONAL AMPLIFIERNew Japan Radio
New Japan Radio
EL1118-G5 PIN LONG CREEPAGE SOP PHOTOTRANSISTOR PHOTOCOUPLEREverlight
Everlight


DataSheet8.cn    |   2020   |  联系我们   |   搜索  |  Simemap