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PDF ( 数据手册 , 数据表 ) 68HC11A0FN

零件编号 68HC11A0FN
描述 MC68HC11A0FN
制造商 Motorola Semiconductors
LOGO Motorola Semiconductors LOGO 


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68HC11A0FN 数据手册, 描述, 功能
MOTOROLAwww.DataSheet4U.com
SEMICONDUCTOR
TECHNICAL DATA
Technical Summary
8-Bit Microcontrollers
Order this document
by MC68HC11A8TS/D
MC68HC11A8
MC68HC11A1
MC68HC11A0
1 Introduction
The MC68HC11A8, MC68HC11A1, and MC68HC11A0 high-performance microcontroller units (MCUs)
are based on the M68HC11 Family. These high speed, low power consumption chips have multiplexed
buses and a fully static design. The chips can operate at frequencies from 3 MHz to dc. The three MCUs
are created from the same masks; the only differences are the value stored in the CONFIG register, and
whether or not the ROM or EEPROM is tested and guaranteed.
For detailed information about specific characteristics of these MCUs, refer to the M68HC11 Reference
Manual (M68HC11RM/AD).
1.1 Features
• M68HC11 CPU
• Power Saving STOP and WAIT Modes
• 8 Kbytes ROM
• 512 Bytes of On-Chip EEPROM
• 256 Bytes of On-Chip RAM (All Saved During Standby)
• 16-Bit Timer System
— 3 Input Capture Channels
— 5 Output Compare Channels
• 8-Bit Pulse Accumulator
• Real-Time Interrupt Circuit
• Computer Operating Properly (COP) Watchdog System
• Synchronous Serial Peripheral Interface (SPI)
• Asynchronous Nonreturn to Zero (NRZ) Serial Communications Interface (SCI)
• 8-Channel, 8-Bit Analog-to-Digital (A/D) Converter
• 38 General-Purpose Input/Output (I/O) Pins
— 15 Bidirectional I/O Pins
— 11 Input-Only Pins and 12 Output-Only Pins (Eight Output-Only Pins in 48-Pin Package)
• Available in 48-Pin Dual In-Line Package (DIP) or 52-Pin Plastic Leaded Chip Carrier (PLCC)
This document contains information on a new product. Specifications and information herein are subject to change without notice.
© MOTOROLA INC., 1991, 1996







68HC11A0FN pdf, 数据表
www.DataSheet4U.com
$0000
$1000
$B600
$E000
$FFFF
SINGLE
CHIP
EXT EXT
EXT EXT
EXT
EXT
EXPANDED
MUX
SPECIAL
BOOTSTRAP
SPECIAL
TEST
Figure 5 Memory Map
0000 256 BYTES RAM
(CAN BE REMAPPED TO ANY
00FF 4K PAGE BY THE INIT REGISTER)
1000 64 BYTE REGISTER BLOCK
(CAN BE REMAPPED TO ANY
4K PAGE BY THE INIT REGISTER)
103F
B600 512 BYTES EEPROM
B7FF
BF40 BOOT
ROM
BFFF
E000 8K ROM
FFFF
BFC0
BFFF
SPECIAL
MODE
INTERRUPT
VECTORS
FFC0
FFFF
NORMAL
MODE
INTERRUPT
VECTORS
MOTOROLA
8
MC68HC11A8
MC68HC11A8TS/D







68HC11A0FN equivalent, schematic
www.DataSheet4U.com
PSEL[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Interrupt Source Promoted
Timer Overflow
Pulse Accumulator Overflow
Pulse Accumulator Input Edge
SPI Serial Transfer Complete
SCI Serial System
Reserved (Default to IRQ)
IRQ
Real-Time Interrupt
Timer Input Capture 1
Timer Input Capture 2
Timer Input Capture 3
Timer Output Compare 1
Timer Output Compare 2
Timer Output Compare 3
Timer Output Compare 4
Timer Output Compare 5
CONFIG — COP, ROM, EEPROM Enables
Bit 7
6
5
4
0000
RESET:
0
0
0
0
$103F
3
NOSEC
2
NOCOP
1
ROMON
Bit 0
EEON
NOTE
The bits of this register are implemented with EEPROM cells. Programming and
erasing follow normal EEPROM procedures. The erased state of CONFIG is $0F.
A new value is not readable until after a subsequent reset sequence. CONFIG can
only be programmed or erased in special modes.
NOSEC — EEPROM Security Disable
Refer to 4 Electrically Erasable Programmable Read-Only Memory (EEPROM).
NOCOP — COP system disable
0 = COP enabled (forces reset on timeout)
1 = COP disabled (does not force reset on timeout)
ROMON — ROM Enable
Refer to 2 Operating Modes and Memory Maps.
EEON — EEPROM Enable
Refer to 2 Operating Modes and Memory Maps.
MOTOROLA
16
MC68HC11A8
MC68HC11A8TS/D










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