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PDF ( 数据手册 , 数据表 ) N80C251SB

零件编号 N80C251SB
描述 (N8xC251SA/SB/SP/SQ) HIGH-PERFORMANCE CHMOS MICROCONTROLLER
制造商 Intel Corporation
LOGO Intel Corporation LOGO 


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N80C251SB 数据手册, 描述, 功能
( DataSheet : www.DataSheet4U.com )
PRELIMINARY
8XC251SA/SB/SP/SQ
HIGH-PERFORMANCE
CHMOS MICROCONTROLLER
Commercial/Express
s Real-time and Programmed Wait State
Bus Operation
s Binary-code Compatible with MCS® 51
s Pin Compatible with 44-pin PLCC and 40-
pin PDIP MCS 51 Sockets
s Register-based MCS® 251 Architecture
— 40-byte Register File
— Registers Accessible as Bytes, Words,
or Double Words
s Enriched MCS 51 Instruction Set
— 16-bit and 32-bit Arithmetic and Logic
Instructions
— Compare and Conditional Jump
Instructions
— Expanded Set of Move Instructions
s Linear Addressing
s 256-Kbyte Expanded External Code/Data
Memory Space
s ROM/OTPROM/EPROM Options:
16 Kbytes (SB/SQ), 8 Kbytes (SA/SP), or
without ROM/OTPROM/EPROM
s 16-bit Internal Code Fetch
s 64-Kbyte Extended Stack Space
s On-chip Data RAM Options:
1-Kbyte (SA/SB) or 512-Byte (SP/SQ)
s 8-bit, 2-clock External Code Fetch in
Page Mode
s Fast MCS 251 Instruction Pipeline
s User-selectable Configurations:
— External Wait States (0-3 wait states)
— Address Range & Memory Mapping
— Page Mode
s 32 Programmable I/O Lines
s Seven Maskable Interrupt Sources
with Four Programmable Priority
Levels
s Three Flexible 16-bit Timer/counters
s Hardware Watchdog Timer
s Programmable Counter Array
— High-speed Output
— Compare/Capture Operation
— Pulse Width Modulator
— Watchdog Timer
s Programmable Serial I/O Port
— Framing Error Detection
— Automatic Address Recognition
s High-performance CHMOS Technology
s Static Standby to 16-MHz Operation
s Complete System Development
Support
— Compatible with Existing Tools
— New MCS 251 Tools Available:
Compiler, Assembler, Debugger, ICE
s Package Options (PDIP, PLCC, and
Ceramic DIP)
A member of the Intel family of 8-bit MCS 251 microcontrollers, the 8XC251SA/SB/SP/SQ is binary-code
compatible with MCS 51 microcontrollers and pin compatible with 40-pin PDIP and 44-pin PLCC MCS 51
microcontrollers. MCS 251 microcontrollers feature an enriched instruction set, linear addressing, and
efficient C-language support. The 8XC251SA/SB/SP/SQ has 512 bytes or 1 Kbyte of on-chip RAM and is
available with 8 Kbytes or 16 Kbytes of on-chip ROM/OTPROM/EPROM, or without ROM/OTPROM/EPROM.
A variety of features can be selected by new user-programmable configurations.
www.DataSheet4U.com
www.DCaOtaPYSRhIeGeHtT4©U.INcToEmL CORPORATION, 1996
May 1996
Order Number: 272783-003







N80C251SB pdf, 数据表
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
PLCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Table 4. 8XC251SA/SB/SP/SQ Pin Assignment
DIP Name
PLCC
DIP
Name
VSS1
1 P1.0/T2
23 VSS2
24 21 A8/P2.0
2 P1.1/T2EX
25 22 A9/P2.1
3 P1.2/ECI
26 23 A10/P2.2
4 P1.3/CEX0
27 24 A11/P2.3
5 P1.4/CEX1
28 25 A12/P2.4
6 P1.5/CEX2
29 26 A13/P2.5
7 P1.6/CEX3/WAIT#
30 27 A14/P2.6
8 P1.7/CEX4/A17/WCLK
31 28 A15/P2.7
9 RST
32 29 PSEN#
10 P3.0/RXD
33 30 ALE/PROG#
VCC2
11 P3.1/TXD
12 P3.2/INT0#
34 VSS2
35 31 EA#/VPP
36 32 AD7/P0.7
13 P3.3/INT1#
37 33 AD6/P0.6
14 P3.4/T0
38 34 AD5/P0.5
15 P3.5/T1
39 35 AD4/P0.4
16 P3.6/WR#
40 36 AD3/P0.3
17 P3.7/RD#/A16
41 37 AD2/P0.2
18 XTAL2
42 38 AD1/P0.1
19 XTAL1
43 39 AD0/P0.0
20 VSS
44 40 VCC
8 PRELIMINARY







N80C251SB equivalent, schematic
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
5.1 D.C. Characteristics
Parameter values apply to all devices unless otherwise indicated.
Symbol
Table 9. DC Characteristics at VCC = 4.5 – 5.5 V
Parameter
Min
Typical
Max
Units Test Conditions
VIL Input Low Voltage
(except EA#)
-0.5
0.2VCC – 0.1
V
VIL1 Input Low Voltage
(EA#)
0
0.2VCC – 0.3
V
VIH
Input High Voltage
0.2VCC + 0.9
(except XTAL1, RST)
VCC + 0.5
V
VIH1 Input High Voltage
(XTAL1, RST)
0.7VCC
VCC + 0.5
V
VOL Output Low Voltage
(Port 1, 2, 3)
0.3
0.45
1.0
V IOL = 100 µA
IOL = 1.6 mA
IOL = 3.5 mA
(Note 1, Note 2)
VOL1
Output Low Voltage
(Port 0, ALE, PSEN#)
0.3
0.45
1.0
V IOL = 200 µA
IOL = 3.2 mA
IOL = 7.0 mA
(Note 1, Note 2)
VOH
Output High Voltage
VCC – 0.3
(Port 1, 2, 3, ALE,
PSEN#)
VCC – 0.7
VCC – 1.5
V IOH = -10 µA
IOH = -30 µA
IOH = -60 µA
(Note 3)
NOTES:
1. Under steady-state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
port 0
26 mA
ports 1–3
15 mA
Maximum Total IOL for
all output pins
71 mA
If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed
to sink current greater than the listed test conditions.
2. Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level
outputs of ALE and ports 1, 2, and 3. The noise is due to external bus capacitance discharging into
the port 0 and port 2 pins when these pins change from high to low. In applications where capacitive
loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to
qualify ALE or other signals with a Schmitt trigger or CMOS-level input logic.
3. Capacitive loading on ports 0 and 2 causes the VOH on ALE and PSEN# to drop below the specifica-
tion when the address lines are stabilizing.
4. Typical values are obtained using VCC = 5.0, TA = 25°C and are not guaranteed.
16 PRELIMINARY










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