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PDF ( 数据手册 , 数据表 ) GVT71256E18

零件编号 GVT71256E18
描述 (GVT71256E18 / GVT7C1325A) 256K x 18 Synchronous Flow Through Burst SRAM
制造商 Cypress Semiconductor
LOGO Cypress Semiconductor LOGO 


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GVT71256E18 数据手册, 描述, 功能
( DataSheet : www.DataSheet4U.com )
325A
CY7C1325A/GVT71256E18
256K x 18 Synchronous Flow-Through Burst SRAM
Features
• Fast access times: 7.5 and 8 ns
• Fast clock speed: 117 and 100 MHz
• Provide high-performance 2-1-1-1 access rate
• Fast OE access times: 4.0 ns
• 3.3V –5% and +10% power supply
• 2.5V or 3.3V I/O supply
• 5V tolerant inputs except I/Os
• Clamp diodes to VSSQ at all inputs and outputs
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
• Three chip enables for depth expansion and address
pipeline
• Address, data and control registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst se-
quence)
• Automatic power-down for portable applications
• Low profile 119-lead, 14-mm x 22-mm BGA (Ball Grid
Array) and 100-pin TQFP packages
Functional Description
The Cypress Synchronous Burst SRAM family employs high-
speed, low-power CMOS designs using advanced triple-layer
polysilicon, double-layer metal technology. Each memory cell
consists of four transistors and two high-valued resistors.
The CY7C1325A/GVT71256E18 SRAM integrates
262,144x18 SRAM cells with advanced synchronous periph-
eral circuitry and a 2-bit counter for internal burst operation. All
synchronous inputs are gated by registers controlled by a pos-
itive-edge-triggered Clock Input (CLK). The synchronous in-
puts include all addresses, all data inputs, address-pipelining
Chip Enable (CE), depth-expansion Chip Enables (CE2 and
CE2), Burst Control inputs (ADSC, ADSP, and ADV), Write
Enables (WEL, WEH, and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and
Burst Mode Control (MODE), and Sleep Mode Control (ZZ).
The data outputs (DQ), enabled by OE, are also asynchro-
nous.
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle. Write cycles can be one to
four bytes wide as controlled by the write control inputs. Indi-
vidual byte write allows individual byte to be written. WEL con-
trols DQ1DQ8 and DQP1. WEH controls DQ9DQ16 and
DQP2. WEL and WEH can be active only with BWE being
LOW. GW being LOW causes all bytes to be written.
The CY7C1325A/GVT71256E18 operates from a +3.3V pow-
er supply and all outputs operate on a +2.5V supply. All inputs
and outputs are JEDEC standard JESD8-5 compatible. The
device is ideally suited for 486, Pentium®, 680x0, and Power-
PCsystems and for systems that benefit from a wide syn-
chronous data bus.
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
7C1325A-117
71256E18-7
7.5
370
10
7C1325A-100
71256E18-8
8
320
10
7C1325A-100
71256E18-9
8
320
10
7C1325A-100
71256E18-10
8
320
10
Pentium is a registered trademark of Intel Corporation.
PowerPC is a trademark of IBM Corporation.
www.DataSheet4U.com
wwCw.yDparteaSssheSeet4mU.iccoomnductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05118 Rev. **
Revised September 12, 2001







GVT71256E18 pdf, 数据表
CY7C1325A/GVT71256E18
Thermal Consideration
Parameter
ΘJA
ΘJC
Description
Thermal Resistance - Junction to Ambient
Thermal Resistance - Junction to Case
Capacitance
Parameter
CI
CO
Description
Input Capacitance[18]
Input/Output Capacitance (DQ)[18]
Conditions
Still air, soldered on 4.25 x 1.125
inch 4-layer PCB
TQFP Typ.
25
9
Unit
°C/W
°C/W
Test Conditions
TA = 25°C, f = 1 MHz,
VCC= 3.3V
Typ. Max.
45
78
Unit
pF
pF
Typical Output Buffer Characteristics
Output High Voltage
VOH (V)
0.5
0
0.8
1.25
1.5
2.3
2.7
2.9
3.4
Pull-up Current
IOH (mA) Min.
38
IOH (mA) Max.
105
38 105
38 105
26 83
20 70
0 30
0 10
00
00
AC Test Loads and Waveforms
Output Low Voltage
VOL (V)
0.5
0
0.4
0.8
1.25
1.6
2.8
3.2
3.4
Pull-down Current
IOL (mA) Min. IΟL (mA) Max.
00
00
10 20
20 40
31 63
40 80
40 80
40 80
40 80
DQ
Z0 = 50
RL = 50
Vt = 1.25V
2.5V
0V
ALL INPUT PULSES
10%
90%
90%
10%
Rise Time:
1 V/ns
Fall Time:
1 V/ns
Note:
18. This parameter is sampled.
Document #: 38-05118 Rev. **
Page 8 of 16







GVT71256E18 equivalent, schematic
CY7C1325A/GVT71256E18
Document Title: CY7C1325A/GVT71256E18 256K x 18 Synchronous Flow-Through Burst SRAM
Document Number: 38-05118
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
108298 09/25/01
BRI New Cypress spec--converted from Galvantech format
Document #: 38-05118 Rev. **
Page 16 of 16










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