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PDF ( 数据手册 , 数据表 ) GVT71256T18

零件编号 GVT71256T18
描述 (GVT71256T18 / GVT7C1359A) 256K X 18 Synchronous-pipelined Cache Tag RAM
制造商 Cypress Semiconductor
LOGO Cypress Semiconductor LOGO 


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GVT71256T18 数据手册, 描述, 功能
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327
CY7C1359A/GVT71256T18
256K x 18 Synchronous-Pipelined Cache Tag RAM
Features
• Fast match times: 3.5, 3.8, 4.0 and 4.5 ns
• Fast clock speed: 166, 150, 133, and 100 MHz
• Fast OE access times: 3.5, 3.8, 4.0 and 5.0 ns
• Pipelined data comparator
• Data input register load control by DEN
• Optimal for depth expansion (one cycle chip deselect
to eliminate bus contention)
• 3.3V –5% and +10% core power supply
• 2.5V or 3.3V I/O supply
• 5V tolerant inputs except I/Os
• Clamp diodes to VSS at all inputs and outputs
• Common data inputs and data outputs
• JTAG boundary scan
• Byte Write Enable and Global Write control
• Three chip enables for depth expansion and address
pipeline
• Address, data, and control registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst se-
quence)
• Automatic power-down for portable applications
• Low-profile JEDEC standard 100-pin TQFP package
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low power CMOS designs using advanced tri-
ple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high valued
resistors.
All synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelin-
ing Chip Enable (CE), depth-expansion Chip Enables (CE2
and CE2), Burst Control Inputs (ADSC, ADSP, and ADV), Write
Enables (WEL, WEH, and BWE), Global Write (GW), and Data
Input Enable (DEN).
Asynchronous inputs include the Burst Mode Control (MODE),
the Output Enable (OE) and the Match Output Enable (MOE).
The data outputs (Q) and Match Output (MATCH), enabled by
OE and MOE respectively, are also asynchronous.
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance pin (ADV).
Data inputs are registered with Data Input Enable (DEN) and
chip enable pins (CE, CE2, and CE2). The outputs of the data
input registers are compared with data in the memory array
and a match signal is generated. The match output is gated
into a pipeline register and released to the match output pin at
the next rising edge of Clock (CLK).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles can be one
to two bytes wide as controlled by the write control inputs. In-
dividual byte write allows individual byte to be written. WEL
controls DQ1DQ9. WEH controls DQ10DQ18. WEL and
WEH can be active only with BWE being LOW. GW being LOW
causes all bytes to be written.
The CY7C1359C/GVT71256T18 operates from a +3.3V pow-
er supply with output power supply being +2.5V or +3.3V. All
inputs and outputs are LVTTL compatible. The device is ideally
suited for address tag RAM for up to 8 MB secondary cache.
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
7C1359A-166
71256T36-6
3.5
310
20
7C1359A-150
71256T36-6.7
3.8
275
20
7C1359A-133
71256T36-7.5
4.0
250
20
7C1359A-100
71256T36-10
4.5
190
20
www.DataSheet4U.com
wwCw.yDparteaSssheSeet4mU.iccoomnductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05120 Rev. **
Revised September 13, 2001







GVT71256T18 pdf, 数据表
CY7C1359A/GVT71256T18
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device
and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the
instruction register. The register is then placed between the
TDI and TDO pins when the controller is moved into Shift-DR
state. Bit 0 in the register is the LSB and the first to reach TDO
when shifting begins. The code is loaded from a 32-bit on-chip
ROM. It describes various attributes of the device as described
in the Identification Register Definitions table.
TAP Controller Instruction Set
Overview
There are two classes of instructions defined in the IEEE Stan-
dard 1149.1-1990; the standard (public) instructions and de-
vice specific (private) instructions. Some public instructions
are mandatory for IEEE 1149.1 compliance. Optional public
instructions must be implemented in prescribed ways.
Although the TAP controller in this device follows the IEEE
1149.1 conventions, it is not IEEE 1149.1 compliant because
some of the mandatory instructions are not fully implemented.
The TAP on this device may be used to monitor all input and
I/O pads, but can not be used to load address, data, or control
signals into the device or to preload the I/O buffers. In other
words, the device will not perform IEEE 1149.1 EXTEST, IN-
TEST, or the preload portion of the SAMPLE/PRELOAD com-
mand.
When the TAP controller is placed in Capture-IR state, the two
least significant bits of the instruction register are loaded with
01. When the controller is moved to the Shift-IR state the in-
struction is serially loaded through the TDI input (while the
previous contents are shifted out at TDO). For all instructions,
the TAP executes newly loaded instructions only when the
controller is moved to Update-IR state. The TAP instruction
sets for this device are listed in the following tables.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is
to be executed whenever the instruction register is loaded with
all 0s. EXTEST is not implemented in this device.
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the device responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is one difference between two instruc-
tions. Unlike SAMPLE/PRELOAD instruction, EXTEST places
the device outputs in a High-Z state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the ID register when the controller is in
Capture-DR mode and places the ID register between the TDI
and TDO pins in Shift-DR mode. The IDCODE instruction is
the default instruction loaded in the instruction upon power-up
and at any time the TAP controller is placed in the test-logic
reset state.
SAMPLE-Z
If the High-Z instruction is loaded in the instruction register, all
output pins are forced to a High-Z state and the boundary scan
register is connected between TDI and TDO pins when the
TAP controller is in a Shift-DR state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is an IEEE 1149.1 mandatory instruction.
The PRELOAD portion of the command is not implemented in
this device, so the device TAP controller is not fully IEEE
1149.1-compliant.
When the SAMPLE/PRELOAD instruction is loaded in the in-
struction register and the TAP controller is in the Capture-DR
state, a snap shot of the data in the devices input and I/O
buffers is loaded into the boundary scan register. Because the
device system clock(s) are independent from the TAP clock
(TCK), it is possible for the TAP to attempt to capture the input
and I/O ring contents while the buffers are in transition (i.e., in
a metastable state). Although allowing the TAP to sample
metastable inputs will not harm the device, repeatable results
can not be expected. To guarantee that the boundary scan
register will capture the correct value of a signal, the device
input signals must be stabilized long enough to meet the TAP
controllers capture setup plus hold time (tCS plus tCH). The
device clock input(s) need not be paused for any other TAP
operation except capturing the input and I/O ring contents into
the boundary scan register.
Moving the controller to Shift-DR state then places the bound-
ary scan register between the TDI and TDO pins. Because the
PRELOAD portion of the command is not implemented in this
device, moving the controller to the Update-DR state with the
SAMPLE/PRELOAD instruction loaded in the instruction reg-
ister has the same effect as the Pause-DR command.
BYPASS
When the BYPASS instruction is loaded in the instruction reg-
ister and the TAP controller is in the Shift-DR state, the bypass
register is placed between TDI and TDO. This allows the board
level scan path to be shortened to facilitate testing of other
devices in the scan path.
Reserved
Do not use these instructions. They are reserved for future
use.
Document #: 38-05120 Rev. **
Page 8 of 24







GVT71256T18 equivalent, schematic
CY7C1359A/GVT71256T18
AC Test Loads and Waveforms
DQ
Z0 = 50
5030 pF
Vt = 1.25V
DQ
1,538
+2.5v
2.5V
1,667
0V
ALL INPUT PULSES
10%
90%
5 pF
1.8 ns
90%
10%
1.8 ns
(a) (b) (c)
(b)
Switching Characteristics Over the Operating Range[27]
-6
166 MHz
-6.7
150 MHz
-7.5
133 MHz
-10
100 MHz
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Clock
tKC Clock Cycle Time
tKF Clock Frequency
tKH Clock HIGH Time
tKL Clock LOW Time
Output Times
6.0 6.7 7.5 8.5 ns
2.4 2.6 2.8 3.4 ns
2.4 2.6 2.8 3.4 ns
tKQ Clock to Output Valid
3.5 3.8 4.0 4.0
tKM Clock to MATCH Valid
tKQX
Clock to Output Invalid
1.5 1.5 1.5 1.5
tKMX
tKQLZ
tKQHZ
tOEQ
tMOEM
tOELZ
tMOELZ
tOEHZ
tMOEHZ
Clock to MATCH Invalid
Clock to Output in Low-Z[17, 28, 29]
0
0
0
0
Clock to Output in High-Z[17, 28, 29] 1.5 6.0 1.5 6.7 1.5 7.5 1.5 8.5
OE to Output Valid[30]
3.5 3.5 3.8 3.8
MOE to MATCH Valid[30]
OE to Output in Low-Z[17, 28, 29]
0
0
0
0
MOE to MATCH in Low-Z[17, 28, 29]
OE to Output in High-Z[17, 28, 29]
3.5 3.5 3.8 3.8
MOE to MATCH in High-Z[17, 28, 29]
Set-up Times
tS
Address, Controls, and Data In[31]
1.5
1.5
1.5
2.0
Hold Times
tH
Address, Controls, and Data In[31]
0.5
0.5
0.5
0.5
Notes:
27. Test conditions as specified with the output loading as shown in part (a) of AC Test Loads unless otherwise noted.
28. Output loading is specified with CL = 5 pF as in AC Test Loads.
29. At any given temperature and voltage condition, tKQHZ is less than tKQLZ, tOEHZ is less than tOELZ and tMOEHZ is less than tMOELZ.
30. OE is a Dont Careafter a write cycle begins To prevent bus contention, OE should be negated prior before the start of write cycle.
31. This is a synchronous device. All synchronous inputs must meet specified set-up and hold time, except for dont careas defined in the truth table.
ns
ns
ns
ns
ns
ns
ns
ns
ns
Document #: 38-05120 Rev. **
Page 16 of 24










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