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PDF ( 数据手册 , 数据表 ) GVT7C1360A

零件编号 GVT7C1360A
描述 (GVT7xxxx) 256K x 36 / 512K x 18 Pipelined SRAM
制造商 Cypress Semiconductor
LOGO Cypress Semiconductor LOGO 


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GVT7C1360A 数据手册, 描述, 功能
( DataSheet : www.DataSheet4U.com )
1CY7C1329
PRELIMINARY
CY7C1360A/GVT71256D36
CY7C1362A/GVT71512D18
256K x 36/512K x 18 Pipelined SRAM
Features
• Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns
• Fast clock speed: 225, 200, 166, and 150 MHz
• Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns
• Optimal for depth expansion (one cycle chip deselect
to eliminate bus contention)
• 3.3V –5% and +10% power supply
• 3.3V or 2.5V I/O supply
• 5V tolerant inputs except I/Os
• Clamp diodes to VSS at all inputs and outputs
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
• Multiple chip enables for depth expansion:
three chip enables for TA package version and two chip
enables for B and T package versions
• Address pipeline capability
• Address, data, and control registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst se-
quence)
• Automatic power-down for portable applications
• JTAG boundary scan for B and T package version
• Low profile 119-bump, 14-mm x 22-mm PBGA (Ball Grid
Array) and 100-pin TQFP packages
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low-power CMOS designs using advanced tri-
ple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high-valued
resistors.
The CY7C1360A/GVT71256D36 and CY7C1362A/
GVT71512D18 SRAMs integrate 262,144x36 and 524,288x18
SRAM cells with advanced synchronous peripheral circuitry
and a 2-bit counter for internal burst operation. All synchro-
nous inputs are gated by registers controlled by a posi-
tive-edge-triggered Clock Input (CLK). The synchronous in-
puts include all addresses, all data inputs, address-pipelining
Chip Enable (CE), depth-expansion Chip Enables (CE2 and
CE2), burst control inputs (ADSC, ADSP, and ADV), Write En-
ables (BWa, BWb, BWc, BWd, and BWE), and global write
(GW). However, the CE2 chip enable input is only available for
the TA package version.
Asynchronous inputs include the Output Enable (OE) and
burst mode control (MODE). The data outputs (Q), enabled by
OE, are also asynchronous.
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance Pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles can be one
to four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BWa
controls DQa. BWb controls DQb. BWc controls DQc. BWd
controls DQd. BWa, BWb, BWc, and BWd can be active only
with BWE being LOW. GW being LOW causes all bytes to be
written. The x18 version only has 18 data inputs/outputs (DQa
and DQb) along with BWa and BWb (no BWc, BWd, DQc, and
DQd).
For the B and T package versions, four pins are used to imple-
ment JTAG test capabilities: Test Mode Select (TMS), Test Da-
ta-In (TDI), Test Clock (TCK), and Test Data-Out (TDO). The
JTAG circuitry is used to serially shift data to and from the
device. JTAG inputs use LVTTL/LVCMOS levels to shift data
during this testing mode of operation. The TA package version
does not offer the JTAG capability.
The CY7C1360A/GVT71256D36 and CY7C1362A/
GVT71512D18 operate from a +3.3V power supply. All inputs
and outputs are LVTTL compatible.
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Commercial
Maximum CMOS Standby Current (mA)
7C1360A-225
71256D36-4.4
7C1362A-225
71512D18-4.4
2.5
570
10
7C1360A-200
71256D36-5
7C1362A-200
71512D18-5
3.0
510
10
7C1360A-166
71256D36-6
7C1362A-166
71512D18-6
3.5
425
10
7C1360A-150
71256D36-6.7
7C1362A-150
71512D18-6.7
3.5
380
10
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wwwC.yDparteaSshseSete4mU.iccoomnductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
May 9, 2001







GVT7C1360A pdf, 数据表
PRELIMINARY
CY7C1360A/GVT71256D36
CY7C1362A/GVT71512D18
Burst Address Table (MODE = NC/VCC)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
A...A00
A...A01
A...A10
A...A11
A...A01
A...A00
A...A11
A...A10
A...A10
A...A11
A...A00
A...A01
A...A11
A...A10
A...A01
A...A00
Burst Address Table (MODE = GND)
First
Address
(external)
A...A00
A...A01
A...A10
A...A11
Second
Address
(internal)
A...A01
A...A10
A...A11
A...A00
Third
Address
(internal)
A...A10
A...A11
A...A00
A...A01
Fourth
Address
(internal)
A...A11
A...A00
A...A01
A...A10
Truth Table[3, 4, 5, 6, 7, 8, 9]
Operation
Address Used CE CE2 CE2 ADSP ADSC ADV WRITE OE CLK
DQ
Deselected Cycle, Power Down None
HX X
X
L X X X L-H High-Z
Deselected Cycle, Power Down None
LX L
L
X X X X L-H High-Z
Deselected Cycle, Power Down None
LH X
L
X X X X L-H High-Z
Deselected Cycle, Power Down None
LX L
H
L X X X L-H High-Z
Deselected Cycle, Power Down None
LH X
H
L X X X L-H High-Z
READ Cycle, Begin Burst
External
LL H
L
X X X L L-H
Q
READ Cycle, Begin Burst
External
LL H
L
X X X H L-H High-Z
WRITE Cycle, Begin Burst
External
LL H
H
L X L X L-H
D
READ Cycle, Begin Burst
External
LL H
H
L X H L L-H
Q
READ Cycle, Begin Burst
External
LL H
H
L X H H L-H High-Z
READ Cycle, Continue Burst Next
XX X
H
H L H L L-H
Q
READ Cycle, Continue Burst Next
XX X
H
HL
H H L-H High-Z
READ Cycle, Continue Burst Next
HX X
X
H L H L L-H
Q
READ Cycle, Continue Burst Next
HX X
X
HL
H H L-H High-Z
WRITE Cycle, Continue Burst Next
XX X
H
HL
L X L-H
D
WRITE Cycle, Continue Burst Next
HX X
X
HL
L X L-H
D
READ Cycle, Suspend Burst Current
XX X
H
H H H L L-H
Q
READ Cycle, Suspend Burst Current
XX X
H
H H H H L-H High-Z
READ Cycle, Suspend Burst Current
HX X
X
H H H L L-H
Q
READ Cycle, Suspend Burst Current
HX X
X
H H H H L-H High-Z
WRITE Cycle, Suspend Burst Current
XX X
H
HH
L X L-H
D
WRITE Cycle, Suspend Burst Current
HX X
X
HH
L X L-H
D
Notes:
3. X = “Don’t Care.” H = logic HIGH. L = logic LOW.
For X36 product, WRITE = L means [BWE + BWa*BWb*BWc*BWd]*GW equals LOW. WRITE = H means [BWE + BWa*BWb*BWc*BWd]*GW equals HIGH.
For X18 product, WRITE = L means [BWE + BWa*BWb]*GW equals LOW. WRITE = H means [BWE + BWa*BWb]*GW equals HIGH.
4. BWa enables write to DQa. BWb enables write to DQb. BWc enables write to DQc. BWd enables write to DQd.
5. All inputs except OE must meet set up and hold times around the rising edge (LOW to HIGH) of CLK.
6. Suspending burst generates wait cycle.l
7. For a write operation following a read operation, OE must be HIGH before the input data required set-up time plus High-Z time for OE and staying HIGH throughout
the input data hold time.
8. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
9. ADSP LOW along with chip being selected always initiates a READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW for
the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification.
8







GVT7C1360A equivalent, schematic
PRELIMINARY
CY7C1360A/GVT71256D36
CY7C1362A/GVT71512D18
Boundary Scan Order (256K x 36)
Signal
Bit# Name TQFP
1 A 44
2 A 45
3 A 46
4 A 47
5 A 48
6 A 49
7 A 50
8 DQa 51
9 DQa 52
10 DQa 53
11 DQa 56
12 DQa 57
13 DQa 58
14 DQa 59
15 DQa 62
16 DQa 63
17 ZZ
64
18 DQb 68
19 DQb 69
20 DQb 72
21 DQb 73
22 DQb 74
23 DQb 75
24 DQb 78
25 DQb 79
26 DQb 80
27 A
81
28 A
82
29 ADV
83
30 ADSP
84
31 ADSC
85
32 OE 86
33 BWE
87
34 GW 88
35 CLK 89
Bump ID
2R
3T
4T
5T
6R
3B
5B
6P
7N
6M
7L
6K
7P
6N
6L
7K
7T
6H
7G
6F
7E
6D
7H
6G
6E
7D
6A
5A
4G
4A
4B
4F
4M
4H
4K
Boundary Scan Order (256K x 36) (continued)
Signal
Bit#
Name
TQFP
Bump ID
36 A 92 6B
37 BWa 93 5L
38 BWb 94 5G
39 BWc 95 3G
40 BWd 96
3L
41 CE2 97 2B
42 CE
98 4E
43 A 99 3A
44 A 100 2A
45 DQc 1 2D
46 DQc 2 1E
47 DQc 3 2F
48 DQc 6 1G
49 DQc 7 2H
50 DQc 8 1D
51 DQc 9 2E
52 DQc 12 2G
53 DQc 13 1H
54 NC 14 5R
55 DQd 18 2K
56 DQd 19 1L
57 DQd 22 2M
58 DQd 23 1N
59 DQd 24 2P
60 DQd 25 1K
61 DQd 28 2L
62 DQd 29 2N
63 DQd 30 1P
64 MODE
31
3R
65 A 32 2C
66 A 33 3C
67 A 34 5C
68 A 35 6C
69 A1
36 4N
70 A0
37 4P
16










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