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PDF ( 数据手册 , 数据表 ) GVT7C1357A

零件编号 GVT7C1357A
描述 (GVT7xxxx) 256K x 36 / 512K x 18 Flow Thru SRAM
制造商 Cypress Semiconductor
LOGO Cypress Semiconductor LOGO 


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GVT7C1357A 数据手册, 描述, 功能
( DataSheet : www.DataSheet4U.com )
1CY7C1357A
CY7C1355A/GVT71256ZB36
PRELIMINARY CY7C1357A/GVT71512ZB18
256Kx36/512Kx18 Flow-Thru SRAM with NoBL™ Architecture
Features
• Zero Bus Latency, no dead cycles between write and
read cycles
• Fast clock speed: 133, 117, and 100 MHz
• Fast access time: 6.5, 7.0, 7.5, and 8.0 ns
• Internally synchronized registered outputs eliminate
the need to control OE
• Single 3.3V –5% and +5% power supply VCC
• Separate VCCQ for 3.3V or 2.5V I/O
• Single R/W (READ/WRITE) control pin
• Positive clock-edge triggered, address, data, and con-
trol signal registers for fully pipelined applications
• Interleaved or linear 4-word burst capability
• Individual byte write (BWa–BWd) control (may be tied
LOW)
• CKE pin to enable clock and suspend operations
• Three chip enables for simple depth expansion
• SNOOZE MODE for low power standby
• JTAG boundary scan
• Low profile 119-bump, 14-mm x 22-mm BGA (Ball Grid
Array) and 100-pin TQFP packages
Functional Description
The CY7C1355A/GVT71256ZB36 and CY7C1357A/
GVT71512ZB18 SRAMs are designed to eliminate dead cy-
cles when transitions from READ to WRITE or vice versa.
These SRAMs are optimized for 100 percent bus utilization
and achieves Zero Bus Latency (ZBL)/No Bus Latency (No-
BL). They integrate 262,144x36 and 524,288x18 SRAM cells,
respectively, with advanced synchronous peripheral circuitry
and a 2-bit counter for internal burst operation. These employ
high-speed, low power CMOS designs using advanced triple-
layer polysilicon, double-layer metal technology. Each memory
cell consists of four transistors and two high valued resistors.
All synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, depth-expansion
Chip Enables (CE, CE2, and CE2), Cycle Start Input (ADV/LD),
Clock Enable (CKE), Byte Write Enables (BWa, BWb, BWc,
and BWd), and read-write control (R/W). BWc and BWd apply
to CY7C1355A/GVT71256ZB36 only.
Address and control signals are applied to the SRAM during
one clock cycle, and one cycle later, its associated data oc-
curs, either read or write.
A Clock Enable (CKE) pin allows operation of the
CY7C1355A/CY7C1357A/GVT71256ZB36/GVT71512ZB18
to be suspended as long as necessary. All synchronous inputs
are ignored when (CKE) is HIGH and the internal device reg-
isters will hold their previous values.
There are three Chip Enable pins (CE, CE2, CE2) that allow
the user to deselect the device when desired. If any one of
these three are not active when ADV/LD is LOW, no new mem-
ory operation can be initiated and any burst cycle in progress
is stopped. However, any pending data transfers (read or write)
will be completed. The data bus will be in high-impedance
state one cycle after chip is deselected or a write cycle is initi-
ated.
The CY7C1355A/GVT71256ZB36 and CY7C1357A/
GVT71512ZB18 have an on-chip 2-bit burst counter. In the
burst mode, the CY7C1355A/GVT71256ZB36 and
CY7C1357A/GVT71512ZB18 provide four cycles of data for a
single address presented to the SRAM. The order of the burst
sequence is defined by the MODE input pin. The MODE pin
selects between linear and interleaved burst sequence. The
ADV/LD signal is used to load a new external address
(ADV/LD=LOW) or increment the internal burst counter
(ADV/LD=HIGH)
Output Enable (OE), Snooze Enable (ZZ) and burst sequence
select (MODE) are the asynchronous signals. OE can be used
to disable the outputs at any given time. ZZ may be tied to LOW
if it is not used.
Four pins are used to implement JTAG test capabilities. The
JTAG circuitry is used to serially shift data to and from the
device. JTAG inputs use LVTTL/LVCMOS levels to shift data
during this testing mode of operation.
Selection Guide
7C1355A-133/
71256ZB36-6.5
7C1357A-133/
71512ZB18-6.5
Maximum Access Time (ns)
6.5
Maximum Operating Current (mA)
410
Maximum CMOS Standby Current (mA)
30
No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation.
7C1355A-117/
71256ZB36-7
7C1357A-117/
71512ZB18-7
7
385
30
7C1355A-100/
71256ZB36-7.5
7C1357A-100/
71512ZB18-7.5
7.5
350
30
7C1355A1-100/
71256ZB36-8
7C1357A1-100/
71512ZB18-8
8
350
30
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wwwC.yDparteaSshseSete4mU.iccoomnductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
May 24, 2001







GVT7C1357A pdf, 数据表
PRELIMINARY
CY7C1355A/GVT71256ZB36
CY7C1357A/GVT71512ZB18
Pin Descriptions (CY7C1357A/GVT71512ZB18) (continued)
512Kx18
TQFP Pins
5, 10, 14, 17,
21, 26, 40, 55,
60, 66, 67, 71,
76, 90
4, 11, 20, 27,
54, 61, 70, 77
1-3, 6, 7, 25,
28-30,
51-53, 56, 57,
75, 78, 79, 84,
95, 96
512Kx18
PBGA Pins
3D, 5D, 3E, 5E,
3F, 5F, 5G, 3H,
5H, 3K, 5K, 3L,
3M, 5M, 3N,
5N, 3P, 5P
1A, 7A, 1F, 7F,
1J, 7J, 1M, 7M,
1U, 7U
4A, 1B, 7B, 1C,
7C, 2D, 4D, 7D,
1E, 6E, 2F, 1G,
6G, 2H, 7H, 3J,
5J, 1K, 6K, 2L,
4L, 7L, 6M, 2N,
7N, 1P, 6P, 1R,
7R, 1T, 4T, 6U
Name
VSS
VCCQ
NC
Type
Ground
Ground: GND.
Description
I/O Supply Output Buffer Supply: +3.3V –0.165V and +0.165V for 3.3V I/O.
+2.5V –0.125V and +0.4V for 2.5V I/O.
- No Connect: These signals are not internally connected. It can
be left floating or be connected to VCC or to GND.
Partial Truth Table for Read/Write[2]
Function
Read
No Write
Write Byte a (DQa)[3]
Write Byte b (DQb)[3]
Write Byte c (DQc)[3]
Write Byte d (DQd}[3]
Write all bytes
R/W
H
L
L
L
L
L
L
BWa
X
H
L
H
H
H
L
BWb
X
H
H
L
H
H
L
BWc[4]
X
H
H
H
L
H
L
BWd[4]
X
H
H
H
H
L
L
Interleaved Burst Address Table
(MODE = VCC or NC)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
A...A00
A...A01
A...A10
A...A11
A...A01
A...A00
A...A11
A...A10
A...A10
A...A11
A...A00
A...A01
Fourth
Address
(internal)[5]
A...A11
A...A10
A...A01
A...A00
Linear Burst Address Table
(MODE = VSS)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
A...A00
A...A01
A...A01
A...A10
A...A10
A...A11
A...A10
A...A11
A...A11
A...A00
A...A00
A...A01
Notes:
2. L means logic LOW. H means logic HIGH. X means “Don’t Care.”
3. Multiple bytes may be selected during the same cycle.
4. BWc and BWd apply to 256Kx36 device only.
5. Upon completion of the Burst sequence, the counter wraps around to its initial state and continues counting.
Fourth
Address
(internal)[5]
A...A11
A...A00
A...A01
A...A10
8







GVT7C1357A equivalent, schematic
PRELIMINARY
CY7C1355A/GVT71256ZB36
CY7C1357A/GVT71512ZB18
Identification Register Definitions
Instruction Field
REVISION NUMBER
(31:28)
DEVICE DEPTH
(27:23)
DEVICE WIDTH
(22:18)
RESERVED
(17:12)
CYPRESS JEDEC ID
CODE (11:1)
ID Register Presence
Indicator (0)
256K x 36
XXXX
00110
00100
XXXXXX
00011100100
1
512K x 18
XXXX
00111
00011
XXXXXX
00011100100
1
Description
Reserved for revision number.
Defines depth of 256K or 512K words.
Defines width of x36 or x18 bits.
Reserved for future use.
Allows unique identification of DEVICE vendor.
Indicates the presence of an ID register.
Scan Register Sizes
Register Name Bit Size (x36)
Instruction
3
Bypass
1
ID 32
Boundary Scan
70
Bit Size (x18)
3
1
32
51
Instruction Codes
Instruction
EXTEST
IDCODE
SAMPLE-Z
RESERVED
SAMPLE/PRELOAD
RESERVED
RESERVED
BYPASS
Code
000
001
010
011
100
101
110
111
Description
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. Forces all device outputs to High-Z state. This instruction is not
IEEE 1149.1-compliant.
Preloads ID register with vendor ID code and places it between TDI and
TDO. This instruction does not affect device operations.
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. Forces all device outputs to High-Z state.
Do not use these instructions; they are reserved for future use.
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. This instruction does not affect device operations. This instruction
does not implement IEEE 1149.1 PRELOAD function and is therefore not
1149.1-compliant.
Do not use these instructions; they are reserved for future use.
Do not use these instructions; they are reserved for future use.
Places the bypass register between TDI and TDO. This instruction does not
affect device operations.
16










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