DataSheet8.cn


PDF ( 数据手册 , 数据表 ) STE100P

零件编号 STE100P
描述 10/100 FAST ETHERNET 3.3V TRANSCEIVER
制造商 ST Microelectronics
LOGO ST Microelectronics LOGO 


1 Page

No Preview Available !

STE100P 数据手册, 描述, 功能
STE100P
10/100 FAST ETHERNET 3.3V TRANSCEIVER
1 DESCRIPTION
The STE100P, also referred to as STEPHY1, is a
high performance Fast Ethernet physical layer inter-
face for 10Base-T and 100Base-TX applications.
It was designed with advanced CMOS technology to
provide a Media Independent Interface (MII) for easy
attachment to 10/100 Media Access Controllers
(MAC) and a physical media interface for 100Base-
TX of IEEE802.3u and 10Base-T of IEEE802.3.
The STEPHY1 supports both half-duplex and full-du-
plex operation, at 10 and 100 Mbps operation. Its op-
erating mode can be set using auto-negotiation,
parallel detection or manual control. It also allows for
the support of auto-negotiation functions for speed
and duplex detection.
2 FEATURES
2.1 Industry standard
IEEE802.3u 100Base-TX and IEEE802.3
10Base-T compliant
Figure 2. Block Diagram
Figure 1. Package
TQFP64 (10x10x1.40mm)
Table 1. Order Codes
Part Number
STE100P
Package
TQFP64
Support for IEEE802.3x flow control
IEEE802.3u Auto-Negotiation support for
10Base-T and 100Base-TX
MII interface
Standard CSMA/CD or full duplex operation
supported
Industrial temperature compliant
LEDS
LEDS
TX_CLK
TXD[3:0]
TX_ER
TX_EN
MDC
MDIO
100Mb/s
4B/5B
TX Channel
Scrambler
Parallel to
Serial
NRZ To NRZI
Encoder
10Mb/s
NRZ To Manchester
Encoder
Link Pulse
Generator
REGISTERS
Auto
Negotiation
Binary To MLT3
Encoder
10 TX
Filter
Loopback
TRANSMITTER
10/100
TXP
TXN
Clock
Generation
System
Clock
RXD[3:0]
RX_ER
RX_DV
RX_CLK
HW
configuration
pins
HW Config
Power Down
100Mb/s
Descrambler
4B/5B Code Align
RX Channel
Serial to
Parallel
NRZI To NRZ
Decoder
Binary To MLT3
Decoder
Clock Recovery
Adaptive
Equalization
BaseLine
Wander
10Mb/s
NRZ To Manchester
Encoder
Link Pulse
Detector
10 TX Filter
Clock Recovery
SMART
Squelch
RECEIVER
10/100
RXP
RXN
September 2004
Rev. 18
1/31







STE100P pdf, 数据表
STE100P
6 REGISTERS AND DESCRIPTORS DESCRIPTION
There are 11 registers with 16 bits each supported for the STE100P. These include 7 basic registers which are
defined according to the clause 22 “Reconciliation Sublayer and Media Independent Interface” and clause 28
“Physical Layer link signaling for 10 Mb/s and 100 Mb/s Auto-Negotiation on twisted pair” of IEEE802.3u stan-
dard.
In addition, there are 4 special registers for advanced chip control and status information.
6.1 Register List
Table 4. Register List
Address
Reg. Index
0 PR0
1 PR1
2 PR2
3 PR3
4 PR4
5 PR5
6 PR6
17 PR17
18 PR18
19 PR19
20 PR20
Name
XCR
XSR
PID1
PID2
ANA
ANLPA
ANE
XCIIS
XIE
100CTR
XMC
Register Descriptions
XCVR Control Register
XCVR Status Register
PHY Identifier 1
PHY Identifier 2
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Ability Register
Auto-Negotiation Expansion Register
XCVR Configuration Information and Interrupt Status Register
XCVR Interrupt Enable Register
100Base-TX PHY Control/Status Register
XCVR Mode Control Register
6.2 Register Descriptions
Table 5. Register Descriptions
Bit #
Name
Descriptions
Default Val RW Type
PR0- XCR, XCVR Control Register. The default values on power-up/reset are as listed below.
15 XRST Reset control.
0 R/W
1: Device will be reset. This bit will be cleared by STE100P
itself after the reset is completed.
14 XLBEN Loop-back mode select.
1: Loop-back mode is selected.
0: Normal mode
0 R/W
13 SPSEL Network Speed select. This bit’s selection will be ignored if 1 R/W
Auto-Negotiation is enabled(bit 12 of PR0 = 1).
1:100Mbps is selected.
0:10Mbps is selected.
12 ANEN Auto-Negotiation ability control.
1: Auto-Negotiation function is enabled.
0: Auto-Negotiation is disabled.
1 R/W
8/31







STE100P equivalent, schematic
STE100P
Data conversion of Parallel to Serial, NRZ to NRZI, NRZI to MLT3: After scrambled, the transmission
data with 5B type in 25MHz will be converted to serial bit stream in 125MHz by the parallel to serial func-
tion. After serialized, the transmission serial bit stream will be further converted from NRZ to NRZI format.
This NRZI conversion function can be bypassed, if the bit 7 of PR19 register is cleared as 0. After NRZI
converted, the NRZI bit stream is passed through MLT3 encoder to generate the TP-PMD specified MLT3
code. With this MLT3 code, it lowers the frequency and reduces the energy of the transmission signal in
the UTP cable and also makes the system easily to meet the FCC specification of EMI.
Wave-Shaper and Media Signal Driver: In order to reduce the energy of the harmonic frequency of trans-
mission signals, the device provides the wave-shaper prior to the line driver to smooth but keep symmetric
the rising/falling edge of transmission signals. The wave-shaped signals include the 100Base-TX and
10Base-T both are passed to the same media signal driver. This design can simplify the external magnetic
connection with single one.
7.2 100Base-TX Receive Operation
Regarding the 100Base-TX receiving operation, the device provides the receiving functions of PMD, PMA, and
PCS for receiving incoming data signals through category 5 UTP cable and an isolation transformer with turns
ratio of 1: 1. It includes the adaptive equalizer and baseline wander, data conversions of MLT3 to NRZI, NRZI
to NRZ and serial to parallel, the PLL for clock and data recovery, the de-scrambler, and the decoder of 5B/4B.
Adaptive Equalizer and Baseline Wander: Since the high speed signals over the unshielded (or shield-
ed) twisted Pair cable will induce the amplitude attenuation and phase shifting. Furthermore, these effects
are depends on the signal frequency, cable type, cable length and the connectors of the cabling. So a re-
liable adaptive equalizer and baseline wander to compensate all the amplitude attenuation and phase shift-
ing are necessary. In the transceiver, it provides the robust circuits to perform these functions.
MLT3 to NRZI Decoder and PLL for Data Recovery: After receiving the proper MLT3 signals, the device
converts the MLT3 to NRZI code for further processing. After adaptive equalizer, baseline wander, and
MLT3 to NRZI decoder, the compensated signals with NRZI type in 125MHz are passed to the Phase Lock
Loop circuits to extract out the original data and synchronous clock.
Data Conversions of NRZI to NRZ and Serial to Parallel: After data is recovered, the signals will be
passed to the NRZI to NRZ converter to generate the 125 MHz serial bit stream. This serial bit stream will
be packed to parallel 5B type for further processing. The NRZI to NRZ conversion can be bypassed, if the
bit 7 of PR19 register is cleared as 0.
De-scrambling and Decoding of 5B/4B: The parallel 5B type data is passed to de-scrambler and 5B/4B
decoder to return their original MII nibble type data.
Carrier sensing: Carrier Sense(CRS) signal is asserted when the STE100P detects any 2 non-contiguous
zeros within any 10 bit boundary of the receiving bit stream. CRS is de-asserted when ESD code-group or
Idle code-group is detected. In half duplex mode, CRS is asserted during packet transmission or receive.
But in full duplex mode, CRS is asserted only during packet reception.
7.3 10Base-T Transmit Operation
This includes the parallel to serial converter, Manchester Encoder, Link test function, Jabber function and the
transmit wave-shaper and line driver described in the section of “Wave-Shaper and Media Signal Driver” of
“100BASE-T Transmission Operation”. It also provides Collision detection and SQE test for half duplex applica-
tion.
7.4 10Base-T Receive Operation
This includes the carrier sense function, receiving filter, PLL for clock and data recovering, Manchester decoder,
and serial to parallel converter.
7.5 Loop-back Operation
The STE100P provides internal loop-back option for both the 100Base-TX and 10Base-T operations. Setting bit
16/31










页数 30 页
下载[ STE100P.PDF 数据手册 ]


分享链接

Link :

推荐数据表

零件编号描述制造商
STE1000-60T4MIWet Tantalum CapacitorsVishay
Vishay
STE10000-10T4MIWet Tantalum CapacitorsVishay
Vishay
STE100APCI 10/100 Ethernet controllerST Microelectronics
ST Microelectronics
STE100N20N-CHANNEL ENHANCEMENT MODE Power MOS TransistorST Microelectronics
ST Microelectronics

零件编号描述制造商
STK15C88256-Kbit (32 K x 8) PowerStore nvSRAMCypress Semiconductor
Cypress Semiconductor
NJM4556DUAL HIGH CURRENT OPERATIONAL AMPLIFIERNew Japan Radio
New Japan Radio
EL1118-G5 PIN LONG CREEPAGE SOP PHOTOTRANSISTOR PHOTOCOUPLEREverlight
Everlight


DataSheet8.cn    |   2020   |  联系我们   |   搜索  |  Simemap