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PDF ( 数据手册 , 数据表 ) ST62E62B

零件编号 ST62E62B
描述 (ST6252B / ST6262B) 8-BIT OTP/EPROM MCUs
制造商 ST Microelectronics
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ST62E62B 数据手册, 描述, 功能
ST62T52B
R ST62T62B/E62B
8-BIT OTP/EPROM MCUs WITH
A/D CONVERTER, AUTO-RELOAD TIMER AND EEPROM
s 3.0 to 6.0V Supply Operating Range
s 8 MHz Maximum Clock Frequency
s -40 to +125°C Operating Temperature Range
s Run, Wait and Stop Modes
s 5 Interrupt Vectors
s Look-up Table capability in Program Memory
s Data Storage in Program Memory:
User selectable size
s Data RAM: 128 bytes
s Data EEPROM: 64 bytes (none on ST62T52B)
s User Programmable Options
s 9 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input
s 5 I/O lines can sink up to 20mA to drive LEDs or
TRIACs directly
s 8-bit Timer/Counter with 7-bit programmable
prescaler
s 8-bit Auto-reload Timer with 7-bit programmable
prescaler (AR Timer)
s Digital Watchdog
s 8-bit A/D Converter with 4 analog inputs
s On-chip Clock oscillator can be driven by Quartz
Crystal Ceramic resonator or RC network
s User configurable Power-on Reset
s One external Non-Maskable Interrupt
s ST626x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port)
DEVICE SUMMARY
DEVICE
ST62T52B
ST62T62B
ST62E62B
EPROM
(Bytes)
1836
OTP
(Bytes)
1836
1836
EEPROM
-
64
64
PDIP16
PSO16
CDIP16W
(See end of Datasheet for Ordering Information)
Rev. 2.4
April 1998
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ST62E62B pdf, 数据表
ST62T52B ST62T62B/E62B
MEMORY MAP (Cont’d)
1.3.3 Data Space
Data Space accommodates all the data necessary
for processing the user program. This space com-
prises the RAM resource, the processor core and
peripheral registers, as well as read-only data
such as constants and look-up tables in
OTP/EPROM.
1.3.3.1 Data ROM
All read-only data is physically stored in program
memory, which also accommodates the Program
Space. The program memory consequently con-
tains the program code to be executed, as well as
the constants and look-up tables required by the
application.
The Data Space locations in which the different
constants and look-up tables are addressed by
the processor core may be thought of as a 64-byte
window through which it is possible to access the
read-only data stored in OTP/EPROM.
1.3.3.2 Data RAM/EEPROM
In ST62T52B, T62B and ST62E62B devices, the
data space includes 60 bytes of RAM, the accu-
mulator (A), the indirect registers (X), (Y), the
short direct registers (V), (W), the I/O port regis-
ters, the peripheral data and control registers, the
interrupt option register and the Data ROM Win-
dow register (DRW register).
Additional RAM and EEPROM pages can also be
addressed using banks of 64 bytes located be-
tween addresses 00h and 3Fh.
1.3.4 Stack Space
Stack space consists of six 12-bit registers which
are used to stack subroutine and interrupt return
addresses, as well as the current program counter
contents.
Table 1. Additional RAM / EEPROM Banks
Device
ST62T52B
ST62T62B
RAM
1 x 64 bytes
1 x 64 bytes
EEPROM
-
1 x 64 bytes
Table 2. ST62T52B, T62B and ST62E62B Data
Memory Space
RAM / EEPROM banks
DATA ROM WINDOW AREA
X REGISTER
Y REGISTER
V REGISTER
W REGISTER
DATA RAM 60 BYTES
PORT A DATA REGISTER
PORT B DATA REGISTER
PORT C DATA REGISTER
RESERVED
PORT A DIRECTION REGISTER
PORT B DIRECTION REGISTER
PORT C DIRECTION REGISTER
RESERVED
INTERRUPT OPTION REGISTER
DATA ROM WINDOW REGISTER
RESERVED
PORT A OPTION REGISTER
PORT B OPTION REGISTER
PORT C OPTION REGISTER
RESERVED
A/D DATA REGISTER
A/D CONTROL REGISTER
TIMER PRESCALER REGISTER
TIMER COUNTER REGISTER
TIMER STATUS CONTROL REGISTER
AR TIMER MODE CONTROL REGISTER
AR TIMER STATUS/CONTROL REGISTER1
AR TIMER STATUS/CONTROL REGISTER2
WATCHDOG REGISTER
AR TIMER RELOAD/CAPTURE REGISTER
AR TIMER COMPARE REGISTER
AR TIMER LOAD REGISTER
OSCILLATOR CONTROL REGISTER
MISCELLANEOUS
RESERVED
DATA RAM/EEPROM REGISTER
RESERVED
EEPROM CONTROL REGISTER
RESERVED
ACCUMULATOR
* WRITE ONLY REGISTER
000h
03Fh
040h
07Fh
080h
081h
082h
083h
084h
0BFh
0C0h
0C1h
0C2h
0C3h
0C4h
0C5h
0C6h
0C7h
0C8h*
0C9h*
0CAh
0CBh
0CCh
0CDh
0CEh
0CFh
0D0h
0D1h
0D2h
0D3h
0D4h
0D5h
0D6h
0D7h
0D8h
0D9h
0DAh
0DBh
0DCh*
0DDh
0DEh
0E7h
0E8h*
0E9h
0EAh
0EBh
0FEh
0FFh
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ST62E62B equivalent, schematic
ST62T52B ST62T62B/E62B
3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES
3.1 CLOCK SYSTEM
The MCU features a Main Oscillator which can be
driven by an external clock, or used in conjunction
with an AT-cut parallel resonant crystal or a suita-
ble ceramic resonator, or with an external resistor
(RNET).
Figure 8. illustrates various possible oscillator con-
figurations using an external crystal or ceramic res-
onator, an external clock input, an external resistor
(RNET). CL1 an CL2 should have a capacitance in the
range 12 to 22 pF for an oscillator frequency in the
4-8 MHz range.
Aprogrammable divider is provided in order to adjust
the internal clock of the MCU to the best power con-
sumption and performance trade-off.
The internal MCU clock frequency (fINT) drives di-
rectly the AR TIMER while it is divided by 12 to
drive the TIMER, the A/D converter and the
Watchdog timer, and by 13 to drive the CPU core,
as may be seen in Figure 9..
With an 8 MHz oscillator frequency, the fastest
machine cycle is therefore 1.625µs.
A machine cycle is the smallest unit of time needed
to execute any operation (for instance, to increment
the Program Counter). An instruction may require
two, four, or five machine cycles for execution.
3.1.1 Main Oscillator
The oscillator configuration may be specified by se-
lecting the appropriate option. When the CRYS-
TAL/RESONATOR option is selected, it must be
used with a quartz crystal, a ceramic resonator or
an external signal provided on the OSCin pin. When
the RC NETWORK option is selected, the system
clock is generated by an external resistor.
Figure 8. Oscillator Configurations
CRYSTAL/RESONATOR CLOCK
CRYSTAL/RESONATOR option
ST6xxx
OSCin
OSCout
CL1n
CL2
EXTERNAL CLOCK
CRYSTAL/RESONATOR option
ST6xxx
OSCin
OSCout
NC
RC NETWORK
RC NETWORK option
ST6xxx
OSCin
NC
OSCout
RNET
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