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PDF ( 数据手册 , 数据表 ) STA015T

零件编号 STA015T
描述 (STA015x) MPEG 2.5 LAYER III AUDIO DECODER WITH ADPCM CAPABILITY
制造商 ST Microelectronics
LOGO ST Microelectronics LOGO 


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STA015T 数据手册, 描述, 功能
STA015
STA015B STA015T
MPEG 2.5 LAYER III AUDIO DECODER
WITH ADPCM CAPABILITY
SINGLE CHIP MPEG2 LAYER 3 DECODER
SUPPORTING:
– All features specified for Layer III in ISO/IEC
11172-3 (MPEG 1 Audio)
– All features specified for Layer III in ISO/IEC
13818-3.2 (MPEG 2 Audio)
m– Lower sampling frequencies syntax exten-
osion, (not specified by ISO) called MPEG 2.5
.cDECODES LAYER III STEREO CHANNELS,
DUAL CHANNEL, SINGLE CHANNEL (MONO)
SUPPORTING ALL THE MPEG 1 & 2
USAMPLING FREQUENCIES AND THE
EXTENSION TO MPEG 2.5:
t448, 44.1, 32, 24, 22.05, 16, 12, 11. 025, 8 KHz
ACCEPTS MPEG 2.5 LAYER III
eELEMENTARY COMPRESSED BITSTREAM
WITH DATA RATE FROM 8 Kbit/s UP TO 320
eKbit/s
hADPCM CODEC CAPABILITIES:
– sample frequency from 8 kHz to 32 kHz
S– sample size from 8 bits to 32 bits
– encoding algorithm: DVI,
taITU-G726 pack (G723-24, G721,G723-40)
– Tone control and fast-forward capability
aEASY PROGRAMMABLE GPSO INTERFACE
FOR ENCODED DATA UP TO 5Mbit/s
.D(TQFP44 & LFBGA 64)
DIGITAL VOLUME CONTROL
DIGITAL BASS & TREBLE CONTROL
wBYPASS MODE FOR EXTERNAL AUDIO
SOURCE
wSERIAL BITSTREAM INPUT INTERFACE
wEASY PROGRAMMABLE ADC INPUT
SO28
TQFP44
LFBGA64
ORDERING NUMBER: STA015$ (SO28)
STA015T$ (TQFP44)
STA015B$ (LFBGA 8x8)
INDICATORS
I2C CONTROL BUS
LOW POWER 2.4V CMOS TECHNOLOGY
WIDE RANGE OF EXTERNAL CRYSTALS
FREQUENCIES SUPPORTED
APPLICATIONS
PC SOUND CARDS
MULTIMEDIA PLAYERS
VOICE RECORDERS
DESCRIPTION
The STA015 is a fully integrated high flexibility
MPEG Layer III Audio Decoder, capable of decod-
ing Layer III compressed elementary streams, as
specified in MPEG 1 and MPEG 2 ISO standards.
The device decodes also elementary streams
compressed by using low sampling rates, as spec-
INTERFACE
ANCILLARY DATA EXTRACTION VIA I2C
INTERFACE.
SERIAL PCM OUTPUT INTERFACE (I2S AND
OTHER FORMATS)
PLL FOR INTERNAL CLOCK AND FOR
OUTPUT PCM CLOCK GENERATION
CRC CHECK AND SYNCHRONISATION
ERROR DETECTION WITH SOFTWARE
March 2004
ified by MPEG 2.5. STA015 receives the input
mdata through a Serial input Interface. The decoded
osignal is a stereo, mono, or dual channel digital
.coutput that can be sent directly to a D/A converter,
Uby the PCM Output Interface.
t4This interface is software programmable to adapt
ethe STA015 digital output to the most common
eDACs architectures used on the market. The func-
htional STA015 chip partitioning is described in
SFig.1a and Fig.1b.
www.Data 1/55







STA015T pdf, 数据表
STA015 STA015B STA015T
CMOS compatibility
The XTI pad low and high levels are CMOS compatible; XTI pad noise margin is better than typical CMOS
pads.
TTL compatibility
The XTI pad low level is compatible with TTL while the high level is not compatible (for example if VDD =
3V TTL min high level = 2.0V while XTI min high level = 2.2V)
2.2 PLL & Clock Generator System
When STA015 receives the input clock, as described in Section 2.1, and a valid layer III input bit stream,
the internal PLL locks, providing to the DSP Core the master clock (DCLK), and to the Audio Output Inter-
face the nominal frequencies of the incoming compressed bit stream. The STA015 PLL block diagram is
described in Figure 5.
The audio sample rates are obtained dividing the oversampling clock (OCLK) by software programmable
factors. The operation is done by STA015 embedded software and it is transparent to the user.
The STA015 PLL can drive directly most of the ommercial DACs families, providing an over sampling
clock, OCLK, obtained dividing the VCO frequency with a software programmable dividers.
Figure 5. PLL and Clocks Generation System
2.3 STA015 Operational Modes
The device can be configured in 4 different operational modes. To select one specific mode a dedicated
CHIP_MODE registers is available. For proper operation the following steps must be issued to switch be-
tween different modes:
– issue a software reset (SOFT_RESET register)
– select the desired mode (CHIP_MODE register)
– run the device (RUN register)
Hereby is a short description of each available mode
ADPCM Encoder
This mode can be used to encode the incoming bitstream with 4 different compression algorithms.
Moreover different sample frequencies and word size are supported. For a detailed escription of this
features refer to the related registers.
ADPCM Decoder
This mode can be used when an ADPCM compressed bitstream must be decoded. The input interface
handling and control flow is the same as in the MP3 Mode.
BYPASS mode
Using this mode it’s possible to use the embedded post-processing controls (volume and tone controls)
to process an incoming uncompressed stereo audio stream. In this configuration ADC input is the only
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STA015T equivalent, schematic
STA015 STA015B STA015T
5.4 READ OPERATION (see Fig. 17)
5.4.1 Current byte address read
The STA015 has an internal byte address counter. Each time a byte is written or read, this counter is in-
cremented. For the current byte address read mode, following a START condition the master sends the
device address with the RW bit set to 1.
The STA015 acknowledges this and outputs the byte addressed by the internal byte address counter. The
master does not acknowledge the received byte, but terminates the transfer with a STOP condition.
5.4.2 Sequential address read
This mode can be initiated with either a current address read or a random address read. However in this
case the master does acknowledge the data byte output and the STA015 continues to output the next byte
in sequence. To terminate the streams of bytes the master does not acknowledge the last received byte,
but terminates the transfer with a STOP condition. The output data stream is from consecutive byte ad-
dresses, with the internal byte address counter automatically incremented after one byte output.
6.0 I2C REGISTERS
The following table gives a description of the MPEG Source Decoder (STA015) register list.
The first column (HEX_COD) is the hexadecimal code for the sub-address.
The second column (DEC_COD) is the decimal code.
The third column (DESCRIPTION) is the description of the information contained in the register.
The fourth column (RESET) inidicate the reset value if any. When no reset value is specifyed, the default
is "undefined".
The fifth column (R/W) is the flag to distinguish register "read only" and "read and write", and the useful
size of the register itself. Each register is 8 bit wide. The master shall operate reading or writing on 8 bits
only.
I2C REGISTERS
HEX_COD
DEC_COD
$00 0
$01 1
$05 5
$06 6
$07 7
$0C 12
$0D 13
$0F 15
$10 16
$13 19
$14 20
$16 22
$18 24
$40 - $51
64 - 81
$40 64
$41 65
$42 66
$43 67
$44 68
DESCRIPTION
VERSION
IDENT
PLLCTL [7:0]
PLLCTL [20:16] (MF[4:0]=M)
PLLCTL [15:12] (IDF[3:0]=N)
REQ_POL
SCLK_POL
ERROR_CODE
SOFT_RESET
PLAY
MUTE
CMD_INTERRUPT
DATA_REQ_ENABLE
ADPCM_DATA_1 to ADPCM_DATA_18
SYNCSTATUS
ANCCOUNT_L
ANCCOUNT_H
HEAD_H[23:16]
HEAD_M[15:8]
RESET
0xAC
0xA1
0x0C
0x00
0x01
0x04
0x00
0x00
0x01
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
R/W
R (8)
R (8)
R/W (8)
R/W (8)
R/W (8)
R/W (8)
R/W (8)
R (8)
W (8)
R/W(8)
R/W(8)
R/W(8)
R/W(8)
R (8)
R (8)
R (8)
R (8)
R(8)
R(8)
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