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PDF ( 数据手册 , 数据表 ) ST93C47T

零件编号 ST93C47T
描述 (ST93C4xx) 1K 64 x 16 or 128 x 8 SERIAL MICROWIRE EEPROM
制造商 ST Microelectronics
LOGO ST Microelectronics LOGO 


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ST93C47T 数据手册, 描述, 功能
ST93C46A,46C,46T
ST93C47C,47T
1K (64 x 16 or 128 x 8) SERIAL MICROWIRE EEPROM
NOT FOR NEW DESIGN
1 MILLION ERASE/WRITE CYCLES, with
40 YEARS DATA RETENTION
DUAL ORGANIZATION: 64 x 16 or 128 x 8
BYTE/WORD and ENTIRE MEMORY
PROGRAMMING INSTRUCTIONS
SELF-TIMED PROGRAMMING CYCLE with
mAUTO-ERASE
oREADY/BUSY SIGNAL DURING
PROGRAMMING
.cSINGLE SUPPLY VOLTAGE:
– 4.5V to 5.5V for ST93C46 version
– 3V to 5.5V for ST93C47 version
USEQUENTIAL READ OPERATION
t45ms TYPICAL PROGRAMMING TIME
ENHANCED ESD/LATCH UP
ePERFORMANCE for ”C” VERSION
ST93C46A, ST93C46C, ST93C46T,
eST93C47C, ST93C47T are replaced by the
M93C46
8
1
PSDIP8 (B)
0.4mm Frame
8
1
SO8 (M)
150mil Width
Figure 1. Logic Diagram
hDESCRIPTION
SThis specification covers a range of 1K bit serial
taEEPROM products, the ST93C46A,46C,46T
specified at 5V±10% and the ST93C47C,47T
specified at 3V to 5.5V.
aIn the text, products are referred to as ST93C46.
The ST93C46 is a 1K bit Electrically Erasable
.DProgrammableMemory (EEPROM) fabricated with
SGS-THOMSON’s High EnduranceSingle Polysili-
con CMOS technology. The memory is accessed
wthrough a serial input (D) and output (Q).
wTable 1. Signal Names
wS Chip Select Input
D
C
S
ORG
VCC
ST93C46
ST93C47
Q
D
Q
C
ORG
VCC
VSS
Serial Data Input
Serial Data Output
Serial Clock
Organisation Select
Supply Voltage
Ground
June 1997
This is information on a product still in production bu t not recommended for new de signs.
wwVSwS .DataSheAIe008t714C 1U/13.com







ST93C47T pdf, 数据表
ST93C46A/46C/46T, ST93C47C/47T
INSTRUCTIONS (cont’d)
(Q = 0) will be returned if S is driven high, and the
ST93C46 will ignore any data on the bus. When the
write cycle is completed, the Ready signal (Q = 1)
will indicate (if S is driven high) that the ST93C46
is ready to receive a new instruction.
The Write instruction includes an automatic Erase
cycle before writing the data, it is therefore unnec-
essary to execute an Erase instruction before a
Write instruction execution.
Erase All
The Erase All instruction (ERAL) erases the whole
memory (all memory bits are set to ”1”). A dummy
address is input during the instruction transfer and
the erase is made in the same way as the ERASE
instruction above. If the ST93C46 is still performing
the write cycle, the Busy signal (Q = 0) will be
returned if S is driven high, and the ST93C46 will
ignore any data on the bus. When the write cycle
is completed, the Ready signal (Q = 1) will indicate
(if S is driven high) that the ST93C46 is ready to
receive a new instruction.
Write All
For correct operation, an ERAL instruction should
be executed before the WRAL instruction.
The Write All instruction (WRAL) writes the Data
Input byte or word to all the addresses of the
memory. In the WRAL instruction, NO automatic
erase is made so all bytes/words must be erased
before the WRAL instruction. If the ST93C46 is still
performing the write cycle, the Busy signal (Q = 0)
will be returned if S is driven high, and the ST93C46
will ignore any data on the bus. When the write
cycle is completed, the Ready signal (Q = 1) will
indicate (if S is driven high) that the ST93C46 is
ready to receive a new instruction.
Figure 7. ERASE, ERAL Sequences
ERASE
S
D
Q
ERASE
ALL
S
D
Q
1 1 1 An A0
CHECK
STATUS
ADDR
OP
CODE
BUSY
READY
1 0 0 1 0 Xn X0
CHECK
STATUS
ADDR
OP
CODE
BUSY
READY
Notes: 1. An: n = 5 for x16 org. and 6 for x8 org.
2. Xn: n = 3 for x16 org. and 4 for x8 org.
8/13
AI00879B














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