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PDF ( 数据手册 , 数据表 ) W134S

零件编号 W134S
描述 (W134M/S) Direct Rambus Clock Generator
制造商 Cypress Semiconductor
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W134S 数据手册, 描述, 功能
W134M/W134S
Direct Rambus™ Clock Generator
Features
Description
• Differential clock source for Direct Rambus™ memory The Cypress W134M/W134S provides the differential clock
subsystem for up to 800-MHz data transfer rate
signals for a Direct Rambus memory subsystem. It includes
• Provide synchronization flexibility: the Rambus®
Channel can optionally be synchronous to an external
system or processor clock
• Power-managed output allows Rambus Channel clock
to be turned off to minimize power consumption for
mmobile applications
• Works with Cypress CY2210, W133, W158, W159, W161,
oand W167 to support Intel® architecture platforms
.c• Low-power CMOS design packaged in a 24-pin QSOP
(150-mil SSOP) package
signals to synchronize the Direct Rambus Channel clock to an
external system clock but can also be used in systems that do
not require synchronization of the Rambus clock.
t4UBlock Diagram
eREFCLK
eMULT0:1
PLL
taShPCLKM
.DaSYNCLKN
Phase
Alignment
Output
Logic
CLK
CLKB
Pin Configuration
VDDIR
REFCLK
VDD
GND
GND
PCLKM
SYNCLKN
GND
VDD
VDDIPD
STOPB
PWRDNB
1
2
3
4
5
6
7
8
9
10
11
12
24 S0
23 S1
22 VDD
21 GND
20 CLK
19 NC
18 CLKB
17 GND
16 VDD
15 MULT0
14 MULT1
13 GND
www .comS0:1
t4USTOPB
Test
Logic
ww.DataSheeCypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
wDocument #: 38-07426 Rev. *C
Revised June 1, 2005







W134S pdf, 数据表
W134M/W134S
Absolute Maximum Conditions[1]
Parameter
VDD, ABS
VI, ABS
Description
Max. voltage on VDD with respect to ground
Max. voltage on any pin with respect ground
Min.
–0.5
–0.5
Max.
4.0
VDD + 0.5
Unit
V
V
External Component Values[2]
Parameter
RS
RP
CF
CMID
Description
Serial Resistor
Parallel Resistor
Edge Rate Filter Capacitor
AC Ground Capacitor
Min.
39
51
4–15[3]
470 pF
Max.
±5%
±5%
±10%
0.1 µF
Unit
pF
±20%
Operating Conditions[4]
Parameter
VDD
TA
tCYCLE,IN
tJ,IN
DCIN
FMIN
PMIN[6]
tCYCLE,PD
tERR,INIT
DCIN,PD
tI,SR
CIN,PD
DCIN,PD
CIN,CMOS
VIL
VIH
VIL,R
VIH,R
VIL,PD
VIH,PD
VDDIR
VDDIPD
Description
Supply Voltage
Ambient Operating Temperature
Refclk Input Cycle Time
Input Cycle-to-Cycle Jitter[5]
Input Duty Cycle over 10,000 Cycles
Input Frequency of Modulation
Modulation Index for Triangular Modulation
Modulation Index for Non-Triangular Modulation
Phase Detector Input Cycle Time at PclkM & SynclkN
Initial Phase error at Phase Detector Inputs
Phase Detector Input Duty Cycle over 10,000 Cycles
Input Slew Rate (measured at 20%-80% of input voltage) for PclkM,
SynclkN, and Refclk
Input Capacitance at PclkM, SynclkN, and Refclk[7]
Input Capacitance matching at PclkM and SynclkN[7]
Input Capacitance at CMOS pins (excluding PclkM, SynclkN, and
Refclk)[7]
Input (CMOS) Signal Low Voltage
Input (CMOS) Signal High Voltage
Refclk input Low Voltage
Refclk input High Voltage
Input Signal Low Voltage for PD Inputs and StopB
Input Signal High Voltage for PD Inputs and StopB
Input Supply Reference for Refclk
Input Supply Reference for PD Inputs
Min.
3.135
0
10
40
30
30
–0.5
25
1
0.7
0.7
0.7
1.235
1.235
Max.
3.465
70
40
250
60
33
0.6
0.5[8]
100
0.5
75
4
7
0.5
10
0.3
0.3
0.3
3.465
2.625
Unit
V
°C
ns
ps
%tCYCLE
kHz
%
%
ns
tCYCLE,PD
tCYCLE,PD
V/ns
pF
pF
pF
VDD
VDD
VDDIR
VDDIR
VDDIPD
VDDIPD
V
V
Notes:
1. Represents stress ratings only, and functional operation at the maximums is not guaranteed.
2. Gives the nominal values of the external components and their maximum acceptable tolerance, assuming ZCH = 28.
3. Do not populate CF. Leave pads for future use.
4. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
5. Refclk jitter measured at VDDIR (nom)/2.
6. If input modulation is used: input modulation is allowed but not required.
7. Capacitance measured at Freq=1 MHz, DC bias = 0.9V and VAC < 100 mV.
8. The amount of allowed spreading for any non-triangular modulation is determined by the induced downstream tracking skew, which cannot exceed the skew
generated by the specified 0.6% triangular modulation. Typically, the amount of allowed non-triangular modulation is about 0.5%.
Document #: 38-07426 Rev. *C
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