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PDF ( 数据手册 , 数据表 ) NQ80220

零件编号 NQ80220
描述 (NQ80220 / NQ80221) Ethernet Media Interface Adapter
制造商 LSI Logic Corporation
LOGO LSI Logic Corporation LOGO 


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NQ80220 数据手册, 描述, 功能
et4U.com 100BASE-MTeXd/1ia08BIn0AteS2rEf2a8-c00Te2/E82A0t0hd/8ea20rp22nt2ee11rt98184
taSheFeatures
s Single Chip 100Base-TX / 10Base-T Physical Layer
aSolution
.Ds Dual Speed - 100/10 Mbps
wws Half And Full Duplex
w s MII Interface To Ethernet Controller
ms MI Interface For Configuration & Status
os Optional Repeater Interface
.cs AutoNegotiation: 10/100, Full/Half Duplex
s Meets All Applicable IEEE 802.3, 10Base-T,
100Base-TX Standards
Us On Chip Wave Shaping - No External Filters
t4Required
s Adaptive Equalizer
es Baseline Wander Correction
es Interface to External 100Base-T4 PHY
s LED Outputs
h- Link
- Activity
S- Collision
- Full Duplex
ta- 10/100
- User Programmable
as Many User Features And Options
s Few External Components
.Ds Pin configuration
- 44L PLCC - 80220
www .com- 64L LQFP - 80221
Note: Check for latest Data Sheet revision
before starting any designs.
SEEQ Data Sheets are now on the Web, at
www.lsilogic.com.
This document is an LSI Logic document. Any
reference to SEEQ Technology should be
considered LSI Logic.
Description
The 80220/80221 are highly integrated analog interface
IC's for twisted pair Ethernet applications. The 80220/
80221 can be configured for either 100 Mbps (100Base-
TX) or 10 Mbps (10Base-T) Ethernet operation. The
80220 is packaged in a 44L package, while the 80221 is
packaged in a 64L package and contains a few more
features.
The 80220/80221 consist of 4B5B/Manchester encoder/
decoder, scrambler/descrambler, 100Base-TX/10Base-T
twisted pair transmitter with wave shaping and output
driver, 100Base-TX/10Base-T twisted pair receiver with
on chip equalizer and baseline wander correction, clock
and data recovery, AutoNegotiation, controller interface
(MII), and serial port (MI).
The addition of internal output waveshaping circuitry and
on-chip filters eliminates the need for external filters nor-
mally required in 100Base-TX and 10Base-T applications.
The 80220/80221 can automatically configure itself for
100 or 10 Mbps and Full or Half Duplex operation with the
on-chip AutoNegotiation algorithm.
The 80220/80221 can access eleven 16-bit registers though
the Management Interface (MI) serial port. These registers
contain configuration inputs, status outputs, and device
capabilities.
The 80220/80221 are ideal as media interfaces for
100Base-TX/10Base-T adapter cards, motherboards, re-
peaters, switching hubs, and external PHY's.
www.DataSheet4U4-11
MD400159/E







NQ80220 pdf, 数据表
80220/80221
Pin Description continued
Pin# Pin
44L 64L
I/O Description
— 28 T4LNK
— 1 NC
5
15
16
17
33
43
44
47
48
49
51
53
64
I
Pullup
100Base-T4 Link Detect Input. This input indicates to the device the link status of
an external 100Base-T4 PHY.
1 = No Detect
0 = 100Base-T4 link Detected from external PHY
No Connect.
MD400159/E
8







NQ80220 equivalent, schematic
80220/80221
3.6.2 10 Mpbs
A scrambler is not used in 10 Mbps mode.
3.6.3 Scrambler Bypass
The scrambler can be bypassed by setting the bypass
scrambler/descrambler bit in the MI serial port Configura-
tion 1 register. When this bit is set, the 5B data bypasses
the scrambler and goes directly from the 4B5B encoder to
the twisted pair transmitter.
3.7 DESCRAMBLER
3.7.1 100 Mbps
The 80220/80221 descrambler takes the scrambled data
from the data recovery block, descrambles it per the IEEE
802.3 specifications, aligns the data on the correct 5B
word boundaries, and sends it to the 4B5B decoder.
The algorithm for synchronization of the descrambler is
the same as the algorithm outlined in the IEEE 802.3
specification. Once the descrambler is synchronized, it
will maintain synchronization as long as enough
descrambled idle pattern 1's are detected within a given
interval. To stay in synchronization, the descrambler
needs to detect at least 25 consecutive descrambled idle
pattern 1's in a 1 mS interval. If 25 consecutive descrambled
idle pattern 1's are not detected within the 1 mS interval,
the descrambler goes out of synchronization and restarts
the synchronization process.
If the descrambler is in the unsynchronized state, the
descrambler loss of synchronization detect bit is set in the
MI serial port Status Output register to indicate this condi-
tion. Once this bit is set, it will stay set until the descrambler
achieves synchronization.
3.7.2 10 Mpbs
A descrambler is not used in 10 Mbps mode.
3.7.3 Descrambler Bypass
The descrambler can be bypassed by setting the bypass
scrambler/descrambler bit in the MI serial port Configura-
tion 1 register. When this bit is set, the data bypasses the
descrambler and goes directly from the TP receiver to the
4B5B decoder.
3.8 TWISTED PAIR TRANSMITTER
3.8.1 Transmitter - 100 Mbps
The transmitter consists of a MLT-3 encoder, waveform
generator and line driver.
The MLT-3 encoder converts the NRZ data from the
scrambler into a three level MLT-3 code required by IEEE
802.3. MLT-3 coding uses three levels and converts 1's to
transitions between the three levels, and converts 0's to no
transitions or changes in level.
The purpose of the waveform generator is to shape the
transmit output pulse. The waveform generator takes the
MLT-3 three level encoded waveform and uses an array of
switched current sources to control the rise/fall time and
level of the signal at the output. The output of the switched
current sources then goes through a low pass filter in order
to "smooth" the current output and remove any high
frequency components. In this way, the waveform gen-
erator preshapes the output waveform transmitted onto
the twisted pair cable to meet the pulse template require-
ments outlined in IEEE 802.3. The waveform generator
eliminates the need for any external filters on the TP
transmit output.
The line driver converts the shaped and smoothed wave-
form to a current output that can drive 100 meters of
category 5 unshielded twisted pair cable or 150 Ohm
shielded twisted pair cable.
3.8.2 Transmitter - 10 Mbps
The transmitter operation in 10 Mbps mode is much
different than the 100 Mbps transmitter. Even so, the
transmitter still consists of a waveform generator and line
driver.
The purpose of the waveform generator is to shape the
output transmit pulse. The waveform generator consists of
a ROM, DAC, clock generator, and filter. The DAC
generates a stair-stepped representation of the desired
output waveform. The stairstepped DAC output then goes
through a low pass filter in order to "smooth" the DAC
output and remove any high frequency components. The
DAC values are determined from the ROM outputs; the
ROM contents are chosen to shape the pulse to the
desired template and are clocked into the DAC at high
speed by the clock generator. In this way, the waveform
generator preshapes the output waveform to be transmit-
ted onto the twisted pair cable to meet the pulse template
requirements outlined in IEEE 802.3 Clause 14 and also
shown in Figure 4. The waveshaper replaces and elimi-
nates external filters on the TP transmit output.
The line driver converts the shaped and smoothed wave-
form to a current output that can drive 100 meters of
category 3/4/5 100 Ohm unshielded twisted pair cable or
150 Ohm shielded twisted pair cable tied directly to the TP
output pins without any external filters. During the idle
period, no output signal is transmitted on the TP outputs
(except link pulse).
MD400159/E
16










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零件编号描述制造商
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