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PDF ( 数据手册 , 数据表 ) NM95MS15

零件编号 NM95MS15
描述 Plug n Play Front-End Devices for ISA-Bus Systems
制造商 National Semiconductor
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NM95MS15 数据手册, 描述, 功能
.com November 1996
NPalMutag95SaMnhSde1Pe5lta4yUFront-End Device for ISA-Bus SystemsGeneral Description
The NM95MS15 is one of the family of single chip solutions
.Ddesigned to provide complete Plug and Play capability for
ISA bus systems The NM95MS15 includes the necessary
w state machine logic to manage the Plug and Play protocol in
w addition to switches for steering Interrupt and DMA re-
quests It also features a built-in 4k bits of serial EEPROM
w for storing the resource data specified in the Plug and Play
Standard In addition 4k bits of the EEPROM is available for
muse by other on-board logic This device provides a truly
complete single-chip solution for implementing Plug and
oPlay on ISA-Bus adapter cards The NM95MS15 supports
two logical devices with a flexible choice of DMA IRQ selec-
.ction I O and MEMORY Chip Select generation
NM95MS15 is implemented using National’s advanced
CMOS process and operates from a single power supply
The NM95MS15 is available in a 64-pin TQFP package
Features
Y Single chip implementation of complete Plug and Play
Standard
Direct interface to ISA-bus
Y Three modes of operation
Normal DMA mode
Extended Interrupt mode
Extended DMA mode
Y 6 8 or 11 ISA-bus interrupt lines and 3 DRQ DACK
lines supported (IRQ’s and DRQ’s are mode
dependent)
Y On-chip EEPROM for resource request table
Y Additional 4k bits of on-chip EEPROM available for ex-
ternal access
Y 24 mA drivers for data outputs
Y 64-pin TQFP package
t4UBlock Diagram
www.DataShee www.DataSheet4U.comC1996NationalSemiconductorCorporation TL D 12394
TL D 12394– 1
RRD-B30M126 Printed in U S A
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NM95MS15 pdf, 数据表
Extended DMA Mode
In the Extended DMA mode support is provided for
A) Two on-board DMA request that is switchable to any
three DMA channels on the ISA bus
B) Two on-board interrupt request lines switchable to any
six IRQ lines on the ISA bus
C) Two programmable I O chip selects for on-board logic
D) Two programmable Memory chip selects for on-board
logic
Figure 3 shows a Block Diagram of NM95MS15 configured
for Extended DMA Mode
FIGURE 3
TL D 12394 – 8
Chip Select Generation
Individual I O or Memory chip select can be generated in
the following two ways
A) Address Decode only
B) Address Decode qualified by Command (IORD IOWR
or SMEMR SMEMW )
On-Chip EEPROM
NM95MS15 has 8k bits of EEPROM on chip All the PnP
resource data structure for the logical device is stored in this
EEPROM Of the 8k bits 4k bits are available for the logical
device’s external usage The logical device can access the
EEPROM through a microwire port which is essentially a
4-wire serial bus The pins CS SK DI DO follow the exact
timing as the standard microwire bus and are compatible to
the NM93Cxx family of EEPROMs
EEPROM Programming
The entire 8k bits of EEPROM can be programmed through
the ISA bus The EEPROM can be programmed by putting
the device (NM95MS15) in the Configuration state (as de-
fined in the PnP standard) Under this state 4 registers at
address 0xF0 – 0xF3 are accessible to program the
EEPROM The data to be programmed is loaded in register
at address 0xF3 and 0xF2 (LSB and MSB respectively) The
address to be programmed is loaded in register at address
0xF1 The Ninth bit of address for 8k bits of memory is
provided through the register at address 0xF0 Both read
write are possible The actual operation does not begin until
Go Ahead (GA) bit is set Programming a word takes ap-
proximately 10 ms The status of the operation can be
polled by the Status bit This bit is set when the operation is
in progress and will be reset when complete The register at
address 0xF0 is the COMMAND register This is the hand-
shake register in programming the EEPROM and is ex-
plained below in a tabular format
COMMAND register 0xF0 Bit 1 0
Bit 2
Bit 6 3
Bit 7
- OP Code bits
GA(Go ahead bits)
If set to 1 the programming will continue
- Reserved should be 0
- It provides A8 of the address A 0 7 is provided by 0xF1 reg
10 - Read operation
01 - Write operation
STATUS register
0x05 Bit 0 - Status Busy bit during programming
‘‘0’’ is busy ‘‘1’’ is done
Address Register 0xF1 Address Register A0– A7
Data Register
0xF2 Data Byte MSB
Data Register
0xF3 Data Byte LSB
The PNP resource data portion of the internal memory is at high address Hence to program that portion bit 7 of register 0xF0 (A8) should be set to 1
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