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PDF ( 数据手册 , 数据表 ) NT256D64S8HA0G-6

零件编号 NT256D64S8HA0G-6
描述 256MB DIMM
制造商 Nanya Technology
LOGO Nanya Technology LOGO 


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NT256D64S8HA0G-6 数据手册, 描述, 功能
NT256D64S8HA0G-6
256MB : 32M x 64
omPC2700 Unbuffered DIMM
U.c184pin Two Bank Unbuffered DDR SDRAM MODULE Based on DDR333 16Mx8 SDRAM
eet4Features
h• 184-Pin Unbuffered 8-Byte Dual In-Line Memory Module
S• 32Mx64 Double Data Rate (DDR) SDRAM DIMM
ta• Performance :
a PC2700
.DSpeed Sort
-6 Unit
wDIMM CAS Latency
2.5 2
wf CK Clock Frequency
166 133 MHz
w t CK Clock Cycle
6 7.5 ns
• DRAM DLL aligns DQ and DQS transitions with clock transitions.
Also aligns QFC transitions with clock during Read cycles
• Address and control signals are fully synchronous to positive
clock edge
• Programmable Operation:
- DIMM CAS Latency: 2, 2.5
- Burst Type: Sequential or Interleave
- Burst Length: 2, 4, 8
f DQ DQ Burst Frequency
333
266 MHz
• Intended for 166 MHz and 133 MHz applications
• Inputs and outputs are SSTL-2 compatible
m• VDD = 2.5Volt ± 0.2, VDDQ = 2.5Volt ± 0.2
o• Single Pulsed RAS interface
• SDRAMs have 4 internal banks for concurrent operation
.c• Module has two physical banks
• Differential clock inputs
• Data is read or written on both clock edges
- Operation: Burst Read and Write
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• 12/10/2 Addressing (row/column/bank)
• 15.6 µs Max. Average Periodic Refresh Interval
• Serial Presence Detect
• Gold contacts
• SDRAMs in 66-pin TSOP Type II Package
t4UDescription
NT256D64S8HA0G-6 is an unbuffered 184-Pin Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module (DIMM),
eorganized as a dual-bank high-speed memory array. The 32Mx64 module is a two-bank DIMM that uses sixteen 16Mx8 DDR
eSDRAMs in 400 mil TSOP packages. The DIMM achieves high-speed data transfer rates of up to 333MHz. The DIMM is intended for use
hin applications operating from 133 MHz to 166 MHz clock speeds with data rates of 266 to 333 MHz. Clock enable CKE0 and / or CKE1
Scontrols all devices on the DIMM.
taPrior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the DIMM by
address inputs A0-A11 and I/O inputs BA0 and BA1 using the mode register set cycle.
aThese DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common
design files minimizes electrical variation between suppliers.
.DThe DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD
data are programmed and locked during module assembly. The last 128 bytes are available to the customer.
wAll NANYA 184 DDR SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25” long space-saving footprint.
wwOrdering Information
Part Number
NT256D64S8HA0G-6
Preliminary, 11/2001
Speed
166MHz (7ns @ CL = 2.5 )
133MHz (7.5ns @ CL= 2 )
.comPC2700
Organization
32Mx64
Leads
Gold
Power
2.5V
w.DataSheet4U1
w © NANYA TECHNOLOGY CORP.
wNANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.







NT256D64S8HA0G-6 pdf, 数据表
NT256D64S8HA0G-6
256MB : 32M x 64
PC2700 Unbuffered DIMM
Operating, Standby, and Refresh Currents
( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)
Symbol
I DD0
I DD1
I DD2P
I DD2N
I DD3P
I DD3N
I DD4R
I DD4W
I DD5
I DD6
Parameter/Condition
Operating Current : one bank; active / precharge; tRC = tRC (MIN) ;
tCK = tCK (MIN) ; DQ, DM, and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle
Operating Current : one bank; active / read / precharge; Burst = 2;
tRC = tRC (MIN) ; CL=2.5; tCK = tCK (MIN) ; IOUT = 0mA;
address and control inputs changing once per clock cycle
Precharge Power-Down Standby Current :
all banks idle; power-down mode; CKE VIL (MAX) ; tCK = tCK (MIN)
Idle Standby Current : CS VIH (MIN) ; all banks idle; CKE >= VIH(MIN) ;
tCK = tCK (MIN) ; address and control inputs changing once per clock cycle
Active Power-Down Standby Current : one bank active;
power-down mode; CKE VIL (MAX) ; tCK = tCK (MIN)
Active Standby Current : one bank; active / precharge; CS VIH (MIN) ;
CKE VIH (MIN) ; tRC = tRAS (MAX) ; tCK = tCK (MIN) ; DQ, DM, and DQS
inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle
Operating Current : one bank; Burst = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
DQ and DQS outputs changing twice per clock cycle; CL = 2.5;
tCK = tCK (MIN) ; IOUT = 0mA
Operating Current : one bank; Burst = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
DQ and DQS inputs changing twice per clock cycle; CL=2.5;
tCK = tCK (MIN)
Auto-Refresh Current :
t RC = t RFC (MIN)
t RC = 15.625 µs
Self-Refresh Current : CKE ?0.2V
PC2700
1160
1360
240
560
240
960
1800
1680
2400
252
32
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2,4
1,2,3
Preliminary, 11/2001
8
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.














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