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PDF ( 数据手册 , 数据表 ) NT256S64V8HC0G

零件编号 NT256S64V8HC0G
描述 256MB SDRAM Module
制造商 Nanya Technology
LOGO Nanya Technology LOGO 


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NT256S64V8HC0G 数据手册, 描述, 功能
NT256S64V8HC0G
256MB : 32M x 64
mUnbuffered SDRAM Module
.co32Mx64 bit Two Bank Unbuffered SDRAM Module
based on 16Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD
et4UFeatures
hel 168-Pin Unbuffered 8-Byte Dual In-Line Memory Module
Sl Intended for PC133 applications
ta- Clock Frequency: 133MHz
a- Clock Cycle: 7.5ns
.D- Clock Assess Time: 5.4ns
l Inputs and outputs are LVTTL (3.3V) compatible
wl Single 3.3V ± 0.3V Power Supply
wl Single Pulsed RAS interface
wl SDRAMs have 4 internal banks
l
l
l
l
Automatic and controlled Precharge commands
Programmable Operation:
- CAS Latency: 2, 3
- Burst Type: Sequential or Interleave
- Burst Length: 1, 2, 4, 8
- Operation: Burst Read and Write or Multiple Burst Read with
Single Write
Suspend Mode and Power Down Mode
4096 Refresh cycles distributed across 64ms
l Module has 2 physical bank
l Fully Synchronous to positive Clock Edge
ml Data Mask for Byte Read/Write control
l Auto Refresh (CBR) and Self Refresh
l Gold contacts
l SDRAMs in TSOP Type II Package
l Serial Presence Detect with Write Protect
.coDescription
NT256S64V8HC0G is unbuffered 168-pin Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which is organized as 32Mx64
Uhigh-speed memory arrays and is configured as two 16M x 64 physical bank. The DIMM uses sixteen 16Mx8 SDRAMs in 400mil TSOP II
pack-ages. The DIMM achieves high-speed data transfer rates of up to 133MHz by employing a prefetch / pipeline hybrid architecture that
t4supports the JEDEC 1N rule while allowing very low burst power.
eAll control, address, and data input/output circuits are synchronized with the positive edge of the externally supplied clock inputs.
All inputs are sampled at the positive edge of each externally supplied clock (CK0 - CK3). Internal operating modes are defined by combinations
eof RAS , CAS , WE , S0 - S3 , DQMB, and CKE0 – CKE1 signals. A command decoder initiates the necessary timings for each operation. A
h14-bit address bus accepts address information in a row / column multiplexing arrangement.
SPrior to any Access operation, the CAS latency, burst type, burst length, and Burst operation type must be programmed into the DIMM by
address inputs A0-A9 during the Mode Register Set cycle. The DIMM uses serial presence detects implemented via a serial EEPROM using
tathe two-pin IIC protocol. The first 128 bytes of serial PD data are used by the DIMM manufacturer. The last 128 bytes are available to the
customer.
.DaOrdering Information
Part Number
wwwNT256S64V8HC0G-7K
MHz.
143MHz
133MHz
133MHz
Speed
CL
3
2
3
t RCD
3
2
3
t RP
3
2
3
Organization
Leads
Power
NT256S64V8HC0G-75B
NT256S64V8HC0G-8B
* CL = CAS Latency
Preliminary 10 / 2001
100MHz
125MHz
100MHz
222
om3 3 3
.c2 2 2
32Mx64
Gold
3.3V
w.DataSheet4U1
w © NANYA TECHNOLOGY CORP.
wNANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.







NT256S64V8HC0G pdf, 数据表
NT256S64V8HC0G
256MB : 32M x 64
Unbuffered SDRAM Module
AC Timing Parameters
Clock and Clock Enable Parameters
Symbol
Parameter
- 7K
Min. Max.
- 75B
Min. Max.
- 8B
Min. Max.
Unit
Note
tCK3
Clock Cycle Time, CAS Latency = 3
7 1000 7.5 1000 8 1000
ns
tCK2
Clock Cycle Time, CAS Latency = 2
7.5 1000 10 1000 10 1000
ns
tAC3(B) Clock Access Time, CAS Latency = 3 - 5.4 - 5.4 - 6 ns
1
tAC2(B) Clock Access Time, CAS Latency = 2 - 5.4 - 6 - 6 ns
1
tCKH
Clock High Pulse Width
2.5 - 2.5 - 3 -
ns
2
tCKL
Clock Low Pulse Width
2.5 - 2.5 - 3 -
ns
2
tCES
Clock Enable Set-up Time
1.5 - 1.5 - 2 -
ns
tCEH
Clock Enable Hold Time
0.8 - 0.8 - 1 -
ns
tSB Power down mode Entry Time
0 7.5 0
7.5 0
12
ns
tT Transition Time (Rise and Fall)
0.5 10 0.5 10 0.5 10
ns
1. Access time is measured at 1.4V. In AC Characteristics section, see notes.
2. t CKH is the pulse width of CLK measured from the positive edge to the negative edge referenced to VIH (min). t CKL is the pulse width of
CLK measured from the negative edge to the positive edge referenced to VIL (max).
Common Parameters
Symbol
Parameter
- 7K
Min. Max.
- 75B
Min. Max.
- 8B
Min. Max.
Unit
Note
tCS Command Setup Time
1.5 - 1.5 - 2 -
ns
tCH Command Hold Time
0.8 - 0.8 - 1 -
ns
tAS Address and Bank Select Set-up Time 1.5 - 1.5 - 2 -
ns
tAH Address and Bank Select Hold Time
0.8 - 0.8 - 1 -
ns
tRCD
RAS to CAS Delay
20 - 20 - 20 -
ns
1
tRC Bank Cycle Time
60 - 67.5 - 70 -
ns
1
tRFC
Auto Refresh to Active/Auto Refresh
60 - 67.5 - 70 -
tRAS
Active Command Period
45 100K 45 100K 50 100K
ns
1
tRP Precharge Time
20 - 20 - 20 -
ns
1
tRRD
Bank to Bank Delay Time
15 - 15 - 20 -
ns
1
tCCD
CAS to CAS Delay Time
1 - 1 - 1 - CLK
1.These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the num
ber of clock cycles = specified value of timing / clock period (count fractions as a whole number).
Mode Register Set Cycle
Symbol
Parameter
- 7K
Min. Max.
- 75B
Min. Max.
- 8B
Min. Max.
Unit
Note
tRSC
Mode Register Set Cycle Time
2 - 2 - 2 - CLK
1
1.These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the num
ber of clock cycles = specified value of timing / clock period (count fractions as a whole number).
Preliminary 10 / 2001
8
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.














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