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PDF ( 数据手册 , 数据表 ) D72001C

零件编号 D72001C
描述 UPD72001C
制造商 NEC
LOGO NEC LOGO 


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D72001C 数据手册, 描述, 功能
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD72001-11, 72001-A8
MULTI-PROTOCOL SERIAL CONTROLLERS
DESCRIPTION
The µPD72001-11 is an MPSC (Multi-Protocol Serial Controller) which is a general-purpose communication LSI
equipped with two sets of bidirectional parallel/serial converter circuits for data communication. This controller has
a transmitter function to convert the parallel data output by a data terminal into serial data and transmit this data to
a data transmission system such as a modem, and a receiver function to convert the serial data output by the data
transmission system into parallel data.
The MPSC can be used with data communications equipment with a variety of communication modes such as the
generally and widely used start-stop synchronization mode, and the HDLC mode which is used for high-speed
communication.
The µPD72001-A8 is a low-voltage model.
For this product, the following documents are separately available. Read these documents as well as this Data
Sheet.
• User’s Manual (S12472E)
(I) (S12753E)
• Application Notes (II) (On preparation)
(III) (On preparation)
FEATURES
• Two sets of parallel/serial circuits supporting three modes: start-stop synchronization, character synchronization,
and bit synchronization modes
Easy application to a system supporting two or more communication protocols such as a protocol converter or
ISDN terminal adapter
• DPLL (Digital Phase Locked Loop), baud rate generator, and crystal oscillation circuit for transmission/reception
clock
Helps reduce cost by decreasing the number of external circuits
• Many variations with power-saving features and small package size
Easy application to portable terminals and high-accuracy portable terminals
The features common to the µPD72001-11 and 72001-A8 are explained as the features of the MPSC in this
document.
The information in this document is subject to change without notice.
Document No. S12184EJ7V0DS00 (7th edition)
Date Published November 1997 N
Printed in Japan
The mark shows major revised points.
©
1997







D72001C pdf, 数据表
µPD72001-11, 72001-A8
Table 1-1. Pin Status at Reset
Pin Name
WR
RD
B/A
C/D
D7 to D0
INT
INTAK
PRI
PRO
DRQTXA
DRQRXA
DTRA/DRQTXB,
DTRB/DRQRXB
TXDA, TXDB
RXDA, RXDB
TRXCA, TRXCB
XI1A/STRXCA
XI1B/STRXCB
XI2A/SYNCA
XI2B/SYNCB
RTSA, RTSB
CTSA, CTSB
DCDA, DCDB
I/O
I
I
I
I
I/O
O
I
I
O
O
O
O
O
I
I/O
I
I/O
O
I
I
RESET (system reset)
High impedance
Depends on PRI
“L”
“L”
DTR function, “H”
Pin Status
Channel reset
High impedance
Depends on PRI
“L”
“L”
Retains current status
“H”
Input status
“H”
Retains current status
Input status
Retains current status
“H” “H”
––
––
– : Undefined
(4) CLK (System Clock) ... Input
This pin inputs the system clock. The input frequency must be five times that of the data transfer rate or higher.
(5) WR (Write) ... Input
This pin inputs a write control signal for control words and transmit data. This pin is active-low.
(6) RD (Read) ... Input
This pin inputs a read control signal for status and receive data. This pin is active-low.
(7) B/A (Channel B/Channel A) ... Input
This pin inputs a signal to select a channel to be accessed when data is written or read. When this pin is “L”,
channel A is selected; when it is “H”, channel B is selected.
(8) C/D (Control/Data) ... Input
This pin inputs a signal that determines the type of the data on the data bus when the data is written or read.
8







D72001C equivalent, schematic
µPD72001-11, 72001-A8
Capacitance (TA = 25 °C, VDD = 0 V)
Parameter
Input capacitance
I/O capacitance
Symbol
CIN
CIO
Condition
fC = 1 MHz
Pins other than test pin: 0 V
AC Characteristics
µPD72001-11 (TA = –40 to +85 °C, VDD = 5 V ± 10 %)
System interface:
Parameter
Symbol
Condition
Clock cycle
tCYK
Clock high-pulse width
tWKH
Clock low-pulse width
tWKL
Clock rise time
tKR 1.5 V 3.0 V
Clock fall time
tKF 3.0 V 1.5 V
Address setup time (vs. RD )
tSAR
Address hold time (vs. RD )
tHRA
RD pulse width
tWRL
Address data output delay time
tDAD TA = –10 to +70 °C
TA = –40 to +85 °C
RD data output delay time
tDRD TA = –10 to +70 °C
TA = –40 to +85 °C
RD data float delay time
tFRD
Address setup time (vs. WR )
tSAW
Address hold time (vs. WR )
tHWA
WR pulse width
tWWL
Data setup time (vs. WR )
tSDW TA = –10 to +70 °C
TA = –40 to +85 °C
Data hold time (vs. WR )
tHWA
Recovery time between RD and WR
tRV
MIN.
MAX.
10
20
Unit
pF
pF
Rated Value
MIN. MAX.
90 2 000
40 1 000
40 1 000
10
10
0
0
120
100
110
100
110
10 85
0
0
120
100
90
0
140
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
16










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