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PDF ( 数据手册 , 数据表 ) WJLXT972A

零件编号 WJLXT972A
描述 Single-Port 10/100 Mbps PHY Transceiver
制造商 Intel
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WJLXT972A 数据手册, 描述, 功能
U.com®
taShIPenHetteY4l TLraXnTs9c7e2iAveSr ingle-Port 10/100 MbpsDatasheet
.Da The Intel® LXT972A Single-Port 10/100 Mbps PHY Transceiver (called hereafter the
w LXT972A Transceiver) directly supports both 100BASE-TX and 10BASE-T applications. The
w LXT972A Transceiver is IEEE compliant and provides a Media Independent Interface (MII) for
easy attachment to 10/100 Media Access Controllers (MACs). The LXT972A Transceiver
w supports full-duplex operation at 10 Mbps and 100 Mbps. Operating conditions for the
mLXT972A Transceiver can be set using auto-negotiation, parallel detection, or manual control.
The LXT972A Transceiver is fabricated with an advanced CMOS process and requires only a
osingle 2.53.3 V power supply with 2.5 V MII interface support.
.cApplications
Combination 10BASE-T/100BASE-TX
UNetwork Interface Cards (NICs)
Network printers
10/100 Personal Computer Memory Card
International Association (PCMCIA) cards
Cable Modems and Set-Top Boxes
t4Product Features
e3.3 V Operation
eLow power consumption (300 mW typical)
h10BASE-T and 100BASE-TX using a
single RJ-45 connection
IEEE 802.3-compliant 10BASE-T or
S100BASE-TX ports with integrated filters
taAuto-negotiation and parallel detection
MII interface with extended register
capability
aRobust baseline wander correction
Carrier Sense Multiple Access / Collision
Detection (CSMA/CD) or full-duplex
operation
JTAG boundary scan
MDIO serial port or hardware pin
configurable
Integrated, programmable LED drivers
64-Pin Low-profile Quad Flat Package
(LQFP)
— LXT972ALC - Commercial (0° to 70 °C
ambient)
www.D .DataSheet4U.comDocument Number: 249186-004
www Revision Date: 25-Oct-2005







WJLXT972A pdf, 数据表
Intel® LXT972A Single-Port 10/100 Mbps PHY Transceiver
Revision History
Page
1
11
95
96
Intel® LXT972A Transceiver Revision 004
Revision Date: 25-Oct-2005
Description
Front page text changed.
Added Table 1 “Related Documents from Intel”
Added Section 10.1, “Top Label Markings”.
Modified Table 57 “Product Ordering Information” and Table 39 “Order Matrix for Intel® LXT972A
Transceiver” under Section 11.0, “Product Ordering Information”.
Page
1
10
11
13
14
15
16
19
24
41
41
45
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46
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48
51
58
71
72
74
Intel® LXT972A Transceiver Revision 003
Revision Date: August 6, 2002
Description
Added “JTAG Boundary Scan” to Product Features on front page.
Modified Figure 1 “LXT972A 64-Pin LQFP Assignments” (replaced TEST1 and TEST0 with GND).
Modified Table 1 “LQFP Numeric Pin List” (replaced TEST1 and TEST0 with GND).
Added note under Section 2.0, “Signal Descriptions”: “Intel recommends that all inputs and multi-
function pins be tied to the inactive states and all outputs be left floating, if unused.”
Modified Table 4 “LXT972A Miscellaneous Signal Descriptions”.
Modified Table 5 “LXT972A Power Supply Signal Descriptions”.
Added Table 8 “LXT972A Pin Types and Modes”.
Added Section 3.2.2.1, “Increased MII Drive Strength”.
Modified Figure 7 “Hardware Configuration Settings”.
Modified Table 13 “Supported JTAG Instructions”.
Modified Table 14 “Device ID Register”.
Modified Table 17 “Absolute Maximum Ratings”.
Modified Table 18 “Operating Conditions”: Added Typ values to Vcc current.
Modified Table 20 “Digital I/O Characteristics - MII Pins”.
Modified Table 22 “I/O Characteristics - LED/CFG Pins”.
Added Table 26 “LXT972A Thermal Characteristics”.
Modified Table 29 “10BASE-T Receive Timing Parameters”.
Modified Table 38 “Register Bit Map” (added Address 26 information).
Added Table 53 “Digital Config Register (Address 26)”.
Modified Table 54 “Transmit Control Register #2 (Address 30)”.
Added Section 8.0, “Product Ordering Information”.
8 Datasheet
Document Number: 249186-004
Revision Date: 25-Oct-2005







WJLXT972A equivalent, schematic
Intel® LXT972A Single-Port 10/100 Mbps PHY Transceiver
4.0 Signal Descriptions for Intel® LXT972A Transceiver
Intel recommends the following configurations for unused pins:
Unused inputs. Configure all unused inputs and unused multi-function pins for inactive states.
Unused outputs. Leave all unused outputs floating.
No connects. Do not use pins designated as NC (no connect), and do not terminate them.
Note: For the tables in this section, the abbreviations listed in Table 3 are used for the “Type” column.
Table 3. Intel® LXT972A Transceiver Signal Types
Abbreviation
A
AI
I
I/O
O
OD
Meaning
Analog
Analog Input
Input
Input/Output
Output
Open Drain
Tables in this section include the following
Table 4, “Intel® LXT972A Transceiver MII Data Interface Signal Descriptions”
Table 5, “Intel® LXT972A Transceiver MII Controller Interface Signal Descriptions”
Table 6, “Intel® LXT972A Transceiver Network Interface Signal Descriptions”
Table 7, “Intel® LXT972A Transceiver Standard Bus and Interface Signal Descriptions”
Table 8, “Intel® LXT972A Transceiver Configuration and LED Driver Signal Descriptions”
Table 9, “Intel® LXT972A Transceiver Power, Ground, No-Connect Signal Descriptions”
Table 10, “Intel® LXT972A Transceiver JTAG Test Signal Descriptions”
Table 11, “Intel® LXT972A Transceiver Pin Types and Modes”
16 Datasheet
Document Number: 249186-004
Revision Date: 25-Oct-2005










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