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PDF ( 数据手册 , 数据表 ) S3076TT

零件编号 S3076TT
描述 Multi-Rate Sonet/SDH Clock Recovery Unit
制造商 Applied Micro Circuits
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S3076TT 数据手册, 描述, 功能
®
mDEVICE
.coSMPEUCLITFIIC-RATAIOTEN SONET/SDH CLOCK RECOVERY UNIT
BMiUCLMTOI-SRAPTEECLSOCNLEOTC/KSDGHECNLEORCAKTORRECOVERY UNIT
S3076
S3076
et4UFEATURES
he• SiGe BiCMOS technology
S• Complies with Bellcore and ITU-T specifica-
tations for jitter tolerance, jitter transfer and
ajitter generation
.D• On-chip high frequency PLL with internal
w loop filter for clock recovery
w • Supports clock recovery for:
w OC-48 (2488.32 Mbps) (with FEC)
Fibre Channel (2125 Mbps) (with FEC)
mOC-24 (1244.16 Mbps) (with FEC)
Gigabit Ethernet (1250 Mbps) (with FEC)
oFibre Channel (1062.5 Mbps) (with FEC)
.cOC-12 (622.08 Mbps) (with FEC)
OC-3 (155.52 Mbps) (with FEC) NRZ data
• Selectable reference frequencies
U19.44 MHz or 155.52 MHz
(or equivalent Fibre Channel/
t4Gigabit Ethernet frequencies)
• Lock detect—monitors frequency of
eincoming data
e• Low-jitter serial interface
• +3.3 V supply
h• Compact 48 pin TQFP TEP package
S• Typical power 620 mW
• Available in Die form also
GENERAL DESCRIPTION
The function of the S3076 clock recovery unit is to
derive high speed timing signals for SONET/SDH-
based equipment. The S3076 is implemented using
AMCC’s proven Phase Locked Loop (PLL) technology.
Figure 1 shows a typical network application.
The S3076 receives an OC-48, OC-24, OC-12, OC-3,
Fibre Channel or Gigabit Ethernet scrambled NRZ sig-
nal with FEC capability up to 8 bytes per 255-byte
block and recovers the clock from the data. The chip
outputs a differential bit clock and retimed data.
The S3076 utilizes an on-chip PLL which consists
of a phase detector, a loop filter, and a Voltage
Controlled Oscillator (VCO). The phase detector
compares the phase relationship between the VCO
output and the serial data input. A loop filter con-
verts the phase detector output into a smooth DC
voltage, and the DC voltage is input to the VCO
whose frequency is varied by this voltage. A block
diagram is shown in Figure 2.
ataFigure 1. System Block Diagram
.D16 16
OTX
ORX S3076
wS3057
w16
w www.DataSheet4U.comS3076 ORX
OTX
S3057
16
October 23, 2000 / Revision A
1







S3076TT pdf, 数据表
S3076
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Table 5. Pin Assignment and Descriptions (Continued)
Pad Assignment (Continued)
Pad #
Pad Center
Pin Name
Pad #
Pad Center
Pin Name
27 (2961.900, 3871.375) BYPASS
40 (651.900, 3871.375)
AVCC
28 (2856.900, 3871.375)
SDN
41 (72.425, 3287.900)
GND
29 (2751.900, 3871.375)
30 (2436.925, 3871.375)
GND
AGND
42 (72.425, 3182.900)
VCC
43
(72.425, 3077.900)
SERCLKOP
31 (2226.900, 3871.375)
32 (2121.900, 3871.375)
AVCC
AVCC
44
(72.425, 2972.900)
SERCLKON
45 (72.425, 2867.900)
VCC
33 (2016.900, 3871.375)
AGND
46 (72.425, 2762.900)
GND
34 (1911.900, 3871.375)
35 (1386.900, 3871.375)
AGND
CAP1
47 (72.425, 1610.400)
48 (72.425, 1505.400)
GND
VCC
36 (1281.900, 3871.375)
CAP2
49
(72.425, 1400.400)
SERDATOP
37 (966.900, 3871.375)
38 (861.900, 3871.375)
AGND
AGND
50
(72.425, 1295.400)
SERDATON
51 (72.425, 1190.400)
VCC
39 (756.900, 3871.375)
AVCC
52 (72.425, 1085.400)
GND
8 October 23, 2000 / Revision A







S3076TT equivalent, schematic
S3076
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Figure 10. +5 V Differential PECL Driver to S3076 Differential CML Input AC Coupled
Termination
+5 V
0.01 µF Zo=50
330
330 0.01 µF Zo=50
Vcc -0.5 V +3.3 V
100
Vcc -0.5 V
S3076
SERDATIP/N
Figure 11. S3076 Differential CML Output to S3057/S3067 Terminations
+3.3 V
S3076
SERDATOP/N
SERCLKOP/N
Zo=50
Zo=50
+3.3 V
Vcc -0.5
100
Vcc -0.5
S3057/S3067
SERDATIP/N
SERCLKIP/N
Figure 12. +5 V Differential PECL Driver to S3076 Reference Clock Input AC Coupled
Termination
+5 V
155 MHz
OSCILLATOR
0.01 µF Zo=50
330
330 0.01 µF Zo=50
Vcc -0.5 V +3.3 V
100
Vcc -0.5 V
S3076
REFCLKP/N
16 October 23, 2000 / Revision A










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