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零件编号 | QL3012 | ||
描述 | qASIC 3 FPGA | ||
制造商 | QuickLogic | ||
LOGO | |||
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QLt3aS0h1e2ept4AUS.cIoCm3 FPGA Data Sheet• • • • • • 12,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance
and High Density
.DaDevice Highlights
wwHigh Performance & High Density
w • 12,000 Usable PLD Gates with 118 I/Os
m• 300 MHz 16-bit Counters,
o400 MHz Datapaths
.c• 0.35 µm four-layer metal non-volatile
CMOS process for smallest die sizes
UEasy to Use / Fast Development
t4Cycles
• 100% routable with 100% utilization and
complete pin-out stability
e• Variable-grain logic cells provide high
eperformance and 100% utilization
• Comprehensive design tools include high
hquality Verilog/VHDL synthesis
Eight Low-Skew Distributed
Networks
• Two array clock/control networks available
to the logic cell flip-flop clock, set and reset
inputs — each driven by an input-only pin
• Two global clock/control networks available
to the logic cell; F1, clock set, reset inputs
and the input, I/O register clock, reset, and
enable inputs as well as the output enable
control — each driven by an input-only or
I/O pin, or any logic cell output or I/O cell
feedback
High Performance
• Input + logic cell + output total delays
under 6 ns
• Data path speeds over 400 MHz
• Counter speeds over 300 MHz
SAdvanced I/O Capabilities
ta• Interfaces with both 3.3 V and 5.0 V devices
• PCI compliant with 3.3 V and 5.0 V buses
afor -1/-2/-3/-4 speed grades
• Full JTAG boundary scan
.D• I/O Cells with individually controlled
Registered Input Path and Output Enables
wTotal of 118 I/O Pins
w• 110 bidirectional input/output pins,
PCI-compliant for 5.0 V and 3.3 V buses for
w m-1/-2/-3/-4 speed grades
.co• Four High Drive input-only pins
U• Four High Drive input-only/distributed
eet4network pins
Figure 1: 320 pASIC 3 Logic Cells
www.DataSh© 2003 QuickLogic Corporation
www.quicklogic.com
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QL3012 pASIC 3 FPGA Data Sheet Rev F
Kv and Kt Graphs
1.1000
1.0800
1.0600
1.0400
1.0200
1.0000
0.9800
0.9600
0.9400
0.9200
3
Voltage Factor vs. Supply Voltage
3.1 3.2 3.3 3.4 3.5
Supply Voltage (V)
Figure 3: Voltage Factor vs. Supply Voltage
3.6
Temperature Factor vs. Operating Temperature
1.15
1.10
1.05
1.00
0.95
0.90
0.85
-60 -40 -20
0
20 40
Junction Temperature C
60
80
Figure 4: Temperature Factor vs. Operating Temperature
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• www.quicklogic.com
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© 2003 QuickLogic Corporation
QL3012 pASIC 3 FPGA Data Sheet Rev F
Contact Information
Telephone:
E-mail:
Support:
Web site:
(408) 990 4000 (US)
(416) 497 8884 (Canada)
+(44) 1932 57 9011 (Rest of Europe)
+(49) 89 930 86 170 (Germany & Benelux)
+(8621) 2890 3029 (Asia)
+(81) 45 470 5525 (Japan)
http://www.quicklogic.com/support
http://www.quicklogic.com/
Revision History
Revision
A
B
C
D
E
F
Table 12: Revision History
Date
Comments
not avail.
First release.
not avail.
not avail
May 2001
Update of AC/DC Specs and reformat
June 2002
Added Kfactor, Power-up, JTAG and mechanical
drawing information. Reformatted.
July 2003
Updated text section in Power-up Sequencing and
Contact information.
Copyright Information
Copyright © 2003 QuickLogic Corporation.
All Rights Reserved.
The information contained in this product brief, and the accompanying software programs
are protected by copyright. All rights are reserved by QuickLogic Corporation. QuickLogic
Corporation reserves the right to make periodic modifications of this product without
obligation to notify any person or entity of such revision. Copying, duplicating, selling, or
otherwise distributing any part of this product without the prior written consent of an
authorized representative of QuickLogic is prohibited.
QuickLogic, QuickWorks, pASIC, and ViaLink are registered trademarks of QuickLogic
Corporation.
Verilog is a registered trademark of Cadence Design Systems, Inc.
All trademarks and registered trademarks are the property of their respective owners.
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www.quicklogic.com
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© 2003 QuickLogic Corporation
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页数 | 16 页 | ||
下载 | [ QL3012.PDF 数据手册 ] |
零件编号 | 描述 | 制造商 |
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