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PDF ( 数据手册 , 数据表 ) NHI15391RT

零件编号 NHI15391RT
描述 (NHI Series) Multi-Protocol Data Bus Interface
制造商 National Hybrid
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NHI15391RT 数据手册, 描述, 功能
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w November 2000
ww mThe information provided in this document is believed to be accurate; however, no responsibility is assumed by NATIONAL
oHYBRID, INC. for its use, and no license or rights are granted by implication or otherwise in connection therewith. Specifications
.care subject to change without notice.
t4U2200 Smithtown Avenue, Ronkonkoma, NY 11779
eeTelephone (631) 981- 2400 Data Bus Fax (631) 981- 2445
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NHI15391RT pdf, 数据表
3.3.1
HOST BUS INTERFACE UNIT
The HBIU provides a standard RAM interface to the host bus. The module performs the following
functions:
Provides NHi- RT device select and decodes host address to select registers.
Transfers data between the NHi-RT and the host (word and byte mode as well as read-
modify- write are supported).
Provides priority input and output for daisy chaining host interrupts.
Outputs *DTACK signal indicating end of bus cycle.
3.3.2
I/O BUS INTERFACE UNIT
The IBIU controls the RAM and I/ O residing on the I/ O bus so that it appears to the host as a
pseudo dual port RAM (i. e., shared memory). The unit implements the following functions:
Arbitrates between host and protocol chip initiated accesses to the RAM and host data
bus.
Decodes address lines to select device (e. g. RAM, external byte- wide I/ O, external
terminal address buffer, command output register).
Generates control signals to access the selected device.
3.3.3
INTERRUPT CONTROL UNIT
The ICU is an 8 input vectored interrupt controller. It contains eight registers as well as a FIFO for
storing pending interrupt vectors.
3.3.3.1 ICU REGISTERS
The ICU contains the following registers
INTERRUPT REQUEST register
INTERRUPT MASK register
INTERRUPT VECTOR register
AUXILIARY VECTOR register
(IRR)
(IMR)
(IVR)
(AVR)
The INTERRUPT REQUEST register samples 8 inputs originating from internal modules. Since
the host can write to this register, all interrupt sequences can be software driven for program
debugging. The inputs and their priorities (level 7 has highest priority) are described in the
following table.
3.3.3.1.1 INTERRUPT DEFINITION TABLE
PRIORITY
0
1
2
3
4
5
6
7
RTU INTERRUPT
VALID TX/RX EOM
INVALID TX/RX EOM
VALID MODE CODE
INVALID MODE CODE
FIFO OVERFLOW
VALID BROADCAST
INVALID BROADCAST
FAILSAFE TIMEOUT
Note: RT Interrupts 5 & 6 are enabled only when separate Broadcast Tables are used.
Masking interrupt 4 creates a revolving Fifo.
As soon as an interrupt is requested, its vector is pushed onto the FIFO - so the chronological
-7-







NHI15391RT equivalent, schematic
4.2.4
INTERRUPT REQUEST
Address: 3(Ubyte) W
The INTERRUPT REQUEST register holds 8 types of interrupt requests (see section on
INTERRUPT CONTROL UNIT for details). Interrupt requests are active high and upon POR the
register is cleared (see initialization section).
15
IRQ7
14
IRQ6
13
IRQ5
12
IRQ4
11
IRQ3
10
IRQ2
9
IRQ1
8
IRQ0
4.2.5
INTERRUPT MASK
Address: 3 Lbyte R/ W
The INTERRUPT MASK register masks the corresponding interrupts. Upon POR, all interrupts
are masked (see initialization section).
7
IMSK7
6
IMSK6
5
IMSK5
4
IMSK4
3
IMSK3
2
IMSK2
1
IMSK1
0
IMSK0
4.2.6
INTERRUPT VECTOR
Address: 3(Ubyte) R
INTERRUPT VECTOR
Address: 4(Lbyte ) R/ W
The IVR is read only in the upper byte at address 3 and is read/ write in the lower byte at address
4. It contains interrupt header information which is popped off the FIFO.
ADDR3(4)
BIT
15(7)
D4
14(6)
D3
13(5)
D2
12(4)
D1
11(3)
D0
9(2) 10(1) 8(0)
L2 L1 L0
The Interrupt Vector register is loaded with LLL data from the fifo when it is popped. The fifo is
popped by a hardware interrupt ackowledge or a read to address 8. This register in undefined at
POR.
L(2: 0)
This is the interrupt priority determined by the message processor.
D(4: 0)
The DDDDD field is inputted by the CPU. This is used as an offset for the interrupt vector. During
a hardware interrupt acknowledge, this register is outputted on the upper and lower bytes of the
CPU data bus.
4.2.7
AUXILIARY VECTOR REGISTER
Address: 4(Ubyte) R
This register contains additional information related to the interrupt request. The data is popped
from the FIFO and latched into the AVR during the interrupt acknowledge cycle or whenever the
FIFO is popped by a host read instruction to address 8. Upon POR, this register is undefined.
MODE
RTU
15
EMP
14
BUS
13 12 11 9 10 8
T/R SADR4 SADR3 SADR2 SADR1 SADR0
MODE4 MODE3 MODE2 MODE1 MODE0
EMP
1= Fifo empty. Ignore data.
0= Fifo data valid. Use data.
Bits: 15
BUS
Bits: 14
0= Indicates that the message was on bus A
1= Indicates that the message was on bus B.
- 15 -










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