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PDF ( 数据手册 , 数据表 ) IZ4406

零件编号 IZ4406
描述 Intelligent 104 Bit EEPROM Conuter for > 20000 Units with Security Logic
制造商 IK Semiconductor
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IZ4406 数据手册, 描述, 功能
m TECHNICAL DATA
U.coIntelligent 104-Bit EEPROM Counter
t4 for > 20000 Units with Security Logic
heeFeatures
S104 x 1 bit organisation
taThree memory areas with special characteristics
a(eg ROM, PROM, EEPROM)
.DMaximum of 20480 count units
Special security features
wMinimum of 104 write/erase cycles
wwData retention for minimum of ten years
Contact configuration and serial interface
in accordance to ISO standard 7816-3
(synchronous transmission)
mPin Definitions and Functions
.coCard Contact
Symbol
Function
C7 I/O Bidirectional data line (open drain)
Code entry on “Input” only for transport
UC3
CLC
Clock input
C2
RST
Control input (reset)
t4C1
VCC
Supply voltage
C6
N.C.
Not connected
eC5
GND
Ground
eIZ4406 comes as an M1 wire-bonded module for embedding in plastic cards and as a die for customer
packaging
hGeneral Description
SThe chip contains an EEPROM/PROM of 88 bits, a mask ROM of 16 bits and a sequencing control with
tasecurity logic (cf block diagram, Fig. 1).
Memory (104 bits) is divided into the following functional areas
aI ROM
This area contains unalterable chip data (eg application, design status).
.DPart of the data is entered by way of a ROM mask and the remainder
when testing. Both parts are unalterable.
II PROM
In this area the user can enter card data for a particular application. A
w control flag can be set to safeguard this area against alteration.
III
PROM/EEPROM
This area contains the count data and stores the current count in
nonvolatile memory. The individual counter stages with carry can be
w erased (ie EEPROM), only the uppermost counter stage not being
w erasable (ie PROM).
mBefore the control flag is set, part of the EEPROM area contains a secret
otransport code. Another part serves as an error counter.
.cFunction of the PROM area:
t4U1 bit: Control flag
3 bits: Test bits for manufacturer
e4 bits: for user
SheIn the condition as supplied, the transport code and the error counter are activated. The chip can only be
taread (except for the transport-code area) and only the error counter can be written.
aFollowing correct entry of the transport code, the entire memory can be read and areas II and III can be
www.Dwritten and EEPROM part of area III can be erased.
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