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PDF ( 数据手册 , 数据表 ) ST6260

零件编号 ST6260
描述 (ST62xxx) 8-BIT OTP/EPROM MCUs
制造商 ST Microelectronics
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ST6260 数据手册, 描述, 功能
ST62T53B/T60B/T63B
R ST62E60B
8-BIT OTP/EPROM MCUs WITH A/D CONVERTER,
AUTO-RELOAD TIMER, EEPROM AND SPI
s 3.0 to 6.0V Supply Operating Range
s 8 MHz Maximum Clock Frequency
s -40 to +125°C Operating Temperature Range
s Run, Wait and Stop Modes
s 5 Interrupt Vectors
s Look-up Table capability in Program Memory
s Data Storage in Program Memory:
User selectable size
s Data RAM: 128 bytes
s DataEEPROM:64/128bytes(none onST62T53B)
s User Programmable Options
s 13 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input
s 6 I/O lines can sink up to 20mA to drive LEDs or
TRIACs directly
s 8-bit Timer/ Counter with 7-bit programmable
prescaler
s 8-bit Auto-reload Timer with 7-bit programmable
prescaler (AR Timer)
s Digital Watchdog
s 8-bit A/D Converter with 7 analog inputs
s 8-bit Synchronous Peripheral Interface (SPI)
s On-chip Clock oscillator can be driven by Quartz
Crystal Ceramic resonator or RC network
s User configurable Power-on Reset
s One external Non-Maskable Interrupt
s ST626x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port).
DEVICE SUMMARY
DEVICE OTP (Bytes)
ST62T53B
ST62T60B
ST62T63B
ST62E60B
1836
3884
1836
-
EPROM
(Bytes)
-
-
-
3884
EEPROM
-
128
64
128
PDIP20
PSO20
CDIP20W
(See end of Datasheet for Ordering Information)
Rev. 2.4
April 1998
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ST6260 pdf, 数据表
ST62T53B/T60B/T63B ST62E60B
MEMORY MAP (Cont’d)
1.3.2 Program Space
Program Space comprises the instructions to be
executed, the data required for immediate ad-
dressing mode instructions, the reserved factory
test area and the user vectors. Program Space is
addressed via the 12-bit Program Counter register
(PC register).
1.3.2.1 Program Memory Protection
The Program Memory in OTP or EPROM devices
can be protected against external readout of mem-
ory by selecting the READOUT PROTECTION op-
tion in the option byte.
Figure 4. ST62E60B/T60B Program
Memory Map
0000h
007Fh
0080h
RESERVED*
In the EPROM parts, READOUT PROTECTION
option can be disactivated only by U.V. erasure
that also results into the whole EPROM context
erasure.
Note: Once the Readout Protection is activated, it
is no longer possible, even for SGS-THOMSON,
to gain access to the OTP contents. Returned
parts with a protection set can therefore not be ac-
cepted.
Figure 5. ST62T53B/T63B Program
Memory Map
0000h
RESERVED*
USER
PROGRAM MEMORY
(O TP/EPRO M)
3872 BYTES
087Fh
0880h
USER
PROGRAM MEMORY
(OT P)
1824 BYTES
0F9Fh
0FA0h
0FEFh
0FF0h
0FF7h
0FF8h
0FF Bh
0FFCh
0FFDh
0FF Eh
0FFF h
RESERVED*
INTERRUPT VECTORS
RESERVED
NMI VECTOR
USER RESET VECTOR
(*) Reserved areas should be filled with 0FFh
0F9Fh
0FA0h
0FEFh
0FF0h
0FF7h
0FF8h
0FFBh
0FFCh
0FFDh
0FFEh
0FFFh
RESERVED*
INTERRUPT VECTORS
RESERVED
NMI VECTOR
USER RESET VECTOR
(*) Reserved areas should be filled with 0FFh
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ST6260 equivalent, schematic
ST62T53B/T60B/T63B ST62E60B
2 CENTRAL PROCESSING UNIT
2.1 INTRODUCTION
The CPU Core of ST6 devices is independent of the
I/O or Memory configuration. As such, it may be
thought of as an independent central processor
communicating with on-chip I/O, Memory and Pe-
ripherals via internal address, data, and control
buses. In-core communication is arranged as
shown in Figure 7; the controller being externally
linked to both the Reset and Oscillator circuits,
while the core is linked to the dedicated on-chip pe-
ripherals via the serial data bus and indirectly, for
interrupt purposes, through the control registers.
2.2 CPU REGISTERS
The ST6 Family CPU core features six registers and
three pairs of flags available to the programmer.
These are described in the following paragraphs.
Accumulator (A). The accumulator is an 8-bit
general purpose register used in all arithmetic cal-
culations, logical operations, and data manipula-
tions. The accumulator can be addressed in Data
space as a RAM location at address FFh. Thus the
ST6 can manipulate the accumulator just like any
other register in Data space.
Figure 7. ST6 Core Block Diagram
Indirect Registers (X, Y). These two indirect reg-
isters are used as pointers to memory locations in
Data space. They are used in the register-indirect
addressing mode. These registers can be ad-
dressed in the data space as RAM locations at ad-
dresses 80h (X) and 81h (Y). They can also be ac-
cessed with the direct, short direct, or bit direct ad-
dressing modes. Accordingly, the ST6 instruction
set can use the indirect registers as any other reg-
ister of the data space.
Short Direct Registers (V, W). These two regis-
ters are used to save a byte in short direct ad-
dressing mode. They can be addressed in Data
space as RAM locations at addresses 82h (V) and
83h (W). They can also be accessed using the di-
rect and bit direct addressing modes. Thus, the
ST6 instruction set can use the short direct regis-
ters as any other register of the data space.
Program Counter (PC). The program counter is a
12-bit register which contains the address of the
next ROM location to be processed by the core.
This ROM location may be an opcode, an oper-
and, or the address of an operand. The 12-bit
length allows the direct addressing of 4096 bytes
in Program space.
RESET
0,01 TO 8MHz
OSCin
OSCout
CONTROLLER
INTERR UPTS
DATA SPACE
OPCOD E
FLAG
VALUES
2
CONTROL
SIGNALS
ADDRESS /READ LINE
DATA
RAM/EEPROM
PRO GRAM
ROM/EPR OM
12
Program Counter
and
6 LAYER STACK
ADDRESS 256
DEC ODER
DATA
ROM/EPROM
A-DATA B-DATA
DED ICATIONS
ACCUMULATOR
F LAGS
ALU
RESULTS TO DATA SPACE (WRITE LINE)
VR01811
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