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PDF ( 数据手册 , 数据表 ) DM74S241

零件编号 DM74S241
描述 (DM74S240 - DM74S244) Octal 3-STATE Buffer/Line Driver/Line Receiver
制造商 Fairchild Semiconductor
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DM74S241 数据手册, 描述, 功能
August 1986
Revised May 2000
DM74S240 DM74S241 DM74S244
Octal 3-STATE Buffer/Line Driver/Line Receiver
General Description
These buffers/line drivers are designed to improve both the
performance and PC board density of 3-STATE buffers/
drivers employed as memory-address drivers, clock driv-
ers, and bus-oriented transmitters/receivers. Featuring 400
mV of hysteresis at each low current PNP data line input,
they provide improved noise rejection and high fanout out-
puts, and can be used to drive terminated lines down to
133.
Features
s 3-STATE outputs drive bus lines directly
s PNP inputs reduce DC loading on bus lines
s Hysteresis at data inputs improves noise margins
s Typical IOL (sink current)
64 mA
s Typical IOH (source current) 15 mA
s Typical propagation delay times
Inverting
4.5 ns
Noninverting 6 ns
s Typical enable/disable times 9 ns
s Typical power dissipation (enabled)
Inverting
450 mW
Noninverting 538 mW
Ordering Code:
Order Number
DM74S240N
DM74S241N
DM74S244N
Package Number
Package Description
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagrams
DM74S240N
DM74S241N
DM74S244N
© 2000 Fairchild Semiconductor Corporation DS006478
www.fairchildsemi.com












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